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Long pytest-xdist runs (e.g. test_mhas_v2 ~2.5k SDPA configs in one worker) hit a much higher GPU memory high-water mark than any single test needs, because the caching allocator retains freed blocks across configs. Setting PYTORCH_CUDA_ALLOC_CONF=expandable_segments:True, garbage_collection_threshold:0.6 before torch is imported reduces the peak to roughly the maximum any single test needs, with no change in wall time or test outcome. Use os.environ.setdefault so user-provided values still win, and place it above the transformer_engine import so the env var is visible by the time torch initializes its CUDA allocator.
Updated the link for DSA in the README to point to the correct directory.
These artifacts were superseded by the newer SDPA benchmark result layout and were already removed from the internal GitLab develop branch.
Two pre-existing bugs in the VariantPackTemplate, plus one defensive guard: 1. Graph copy -> dangling host pointers. template_ptrs stores raw addresses into cached_pass_by_value storage owned by the source Graph. Default copy propagated prepared=true while the addresses still pointed at the source. Fix: VarpackPrepStateBox copy ctor/assign now always start with prepared=false so the copy re-preps on first use against its own storage. 2. Re-deserialize on the same Graph -> stale template. deserialize(handle,...) rebinds cached_pass_by_value but the existing prepared=true causes the eager prep to short-circuit, leaving the slot layout from the prior deserialize. Fix: reset prepared=false and clear varpack_template before the eager prep call. 3. Null device_ptrs in raw-ptr create_variant_pack overloads. Reject nullptr + non-empty uids instead of forwarding to the cuDNN backend. Adds explicit null-plan guards across detail::execute overloads, returning GRAPH_EXECUTION_FAILED with "No plan found to execute!" instead of dereferencing plan via plan->getTag(). Ports https://gitlab-master.nvidia.com/cudnn/cudnn_frontend/-/merge_requests/2117 Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
Addresses review feedback on PR #248: the prior fix reset prepared=false and varpack_template but left deserialized_tensor_properties, deserialized_pass_by_value, deserialized_workspace_modifications, and tensors_to_dump populated from any earlier deserialize(handle, old_data). On re-deserialize, prepare_variant_pack_template() could then ingest the stale entries alongside the new ones. Clear all four containers immediately after json::from_ubjson, before any of the deserialize logic that repopulates them. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
Signed-off-by: Ziang Li <ziangli@umich.edu>
Signed-off-by: Ziang Li <ziangli@umich.edu>
…inning (#259) * feat(python): add get_engine_and_knobs_at_index for structured plan pinning get_plan_name_at_index returns a formatted "engN_kT=V" tag built from the engine global index and knob choices. Callers that want to persist a tuned plan and replay it later are forced to either store the bare plan index (which drifts when the policy=ALL plan list is re-enumerated across cudnn-frontend / backend versions) or parse the tag string. Expose the structured data directly: get_engine_and_knobs_at_index returns (engine_id, {KnobType_t: value}), reading the same backend attributes get_engine_tag stringifies. The result feeds straight into create_execution_plan(engine_id, knobs) to rebuild the exact same kernel on a fresh graph without a heuristics query. - detail::get_engine_id_and_knobs (cudnn_frontend_utils.h): structured reader - Execution_plan_list::get_engine_and_knobs_at_index (plans.h) - Graph::get_engine_and_knobs_at_index (graph_interface.h) - PyGraph binding (pygraph.h/.cpp) Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com> * address review: bounds-check index, add cpp unit test, trim comments - get_engine_and_knobs_at_index: reject out-of-range index (mirrors check_support_at_index) instead of indexing engine_configs OOB. - add test/cpp/get_engine_and_knobs.cpp: enumerate a matmul graph's plans, read (engine_id, knobs) for each, and confirm re-pinning via create_execution_plan reproduces the same plan (matching name); also checks out-of-range indices error. - trim the new doc comments to match neighboring style. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com> * knobs: add SWAP_AB / INPUT_TMA_ENABLE / OUTPUT_TMA_ENABLE to KnobType_t KnobType_t (and the to/from backend converters) stopped at WARP_SPEC_CFG (42), so engines using SWAP_AB (43, cuDNN 9.18), INPUT_TMA_ENABLE (44) or OUTPUT_TMA_ENABLE (45, cuDNN 9.22) had those knobs mapped to NOT_SET by convert_from_backend_knob_type. Feeding NOT_SET back into create_execution_plan then failed convert_to_backend_knob_type with INVALID_VALUE -- so a plan enumerated with one of these knobs (e.g. via get_engine_and_knobs_at_index) could not be pinned. Add the three knob types to the enum, both converters (version-gated to match the backend @SInCE), and the pybind knob_type enum. The cpp test now compares the structured identity (engine id + knob map) instead of the plan-name tag, since the tag serializes knobs in engine-config order, which differs between the heuristic config and the pinned one even though the kernel is identical. create_execution_plan is now asserted to succeed for every enumerated plan; building it stays best-effort (can fail for unrelated environment reasons such as a ptxas older than the engine's target). Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com> * make get_engine_tag deterministic: sort knob choices by type The plan-name tag was built by iterating CUDNN_ATTR_ENGINECFG_KNOB_CHOICES in stored order, which differs between the heuristics path and create_execution_plan (set_knob_choices iterates a std::unordered_map). So the same engine + knob values could serialize to differently-ordered tags (e.g. eng11_k2=29_k27=0...k43=0 vs eng11_k43=0_k38=0...k2=29) -- the kernel is identical but the string isn't a stable id. Sort the knob choices by type before formatting so the tag is a deterministic function of the engine config regardless of how it was built. This is off the execution hot path (tag is used for logging / plan identity), so no perf impact; the actual knob choices passed to the backend are unchanged. The cpp test now also asserts the pinned plan's tag matches the original's. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com> --------- Co-authored-by: Yang Xu <yanxu@nvidia.com> Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
* update sdpa benchmark artifacts * update acknowledgement
…IB_NAME When dynamic loading is enabled, load_cudart_so() searches for the supported libcudart major versions and aborts with "Multiple libcudart libraries found" when more than one is visible on the library search path. This happens in containerized environments such as GKE, where the TCPXO NCCL plugin mounts a different libcudart major version from the host than the one shipped in the container. Check the CUDNN_FRONTEND_CUDART_LIB_NAME environment variable first; when set to a library name or path, dlopen exactly that library and skip the automatic multi-version detection. Behavior is unchanged when the variable is unset. Fixes #267 Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
… Perfsim, HACK/Ugly, STS/CGA SASS terms) (#273) Comment-only cleanups, no behaviour change. Replaces guardword-flagged phrasing with neutral equivalents in 7 files: - attention_utils.h:67 — drop internal `xmma/fast_math.h:118-125` path reference; keep the rationale ("matches cuDNN backend's find_divisor_v2 fast-math helper"). - test_sdpa_bwd.py:8 — drop `gitlab-master.nvidia.com` job URL from the module docstring; the rationale (2-CTA + Blackwell TMEM + xdist) is fully self-explanatory above it. - dense_score_recompute_sm90.py — "Perfsim" → "Profiling"; "Weights/LSE LDG" → "Weights/LSE load-from-global" (x2). - indexer_backward_sm90.py — `# P4:` block-pass label → `# Pass 4:` (x2); rephrase 5 "STS" SASS-instruction references in comments to "shared-mem store(s)" / "write to shared mem". - indexer_backward_sm100.py — same STS → shared-mem-store rephrasing in 1 docstring. - dsa_bwd_sm90.py:386 — `# HACK:` → `# Note:` (same meaning). - dsa_bwd_sm90.py:1554 — `STS(dS)` → "storing dS to shared mem". - dsa_bwd_sm100.py:941 — `# Ugly,` → `# Awkward,`. - dense_gemm_persistent_swiglu.py:1049 — "single CGA" → "single cluster". Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
The Windows wheel build (deploy:build_bdist_wheels_3.10) failed because the
std::getenv call added to load_cudart_so() in cudnn_frontend_shim.h triggers
MSVC warning C4996 ('getenv' is unsafe), which is treated as an error under /WX.
Root cause and fixes:
- Move get_environment() to cudnn_frontend_shim.h (the lowest-level header,
included by utils.h before Logging.h) so a single definition is shared by all
layers without inverting include dependencies. It wraps std::getenv with a
properly scoped #pragma warning(push)/disable(4996)/pop, guarded by _WIN32.
- Route all getenv call sites through get_environment(): shim.h, graph_properties.h,
scaled_dot_product_flash_attention.h, and sm100_rms_norm_silu_engine.h. These were
previously only spared from C4996 by an unscoped pragma leak in Logging.h, and would
have started failing once that leak was fixed.
- Remove the duplicate get_environment() from cudnn_frontend_Logging.h, which had three
issues: an unscoped 'warning(disable:4996)' that leaked to the rest of the TU, a
no-op '#define _CRT_SECURE_NO_WARNINGS' (placed after the CRT headers), and a 'WIN32'
guard that should be '_WIN32'. Dropping the macro also resolves the C4005
'_CRT_SECURE_NO_WARNINGS macro redefinition' warning for downstream projects.
Fixes #139
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
… are found Loading cudart no longer aborts when both libcudart.so.12 and libcudart.so.13 are present in the library search path. Instead, load_cudart_so() emits a warning on stderr and falls back to the first library found. Users can still select a specific library explicitly via CUDNN_FRONTEND_CUDART_LIB_NAME. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
* Promote L1 Python tests to L0 * Restore L1 markers except FP8 ragged backward
Adds optional group_offset support to the reduction node so cuDNN FE can express per-expert reductions for MoE grouped GEMM workloads. - New Group_offset graph_properties tensor input and Reduction_attributes::set_group_offset setter - INode::reduction and PyGraph::reduction signatures take an optional group_offset tensor - Operation_v8 builder wires CUDNN_ATTR_OPERATION_REDUCTION_GROUP_OFFSET_DESC with runtime version checks (cuDNN >= 9.24.0) - Python binding (pygraph) exposes the optional group_offset argument Mirrors gitlab-master cudnn/cudnn_frontend MR !2111 by @yanqinz. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
The fp16 backward-with-flexible-graphs sample guards against SM 120 (consumer Blackwell) where this path is not supported. The guard used an exact == 120 check, which missed SM 121 (GB10 / DGX Spark) and any later consumer Blackwell arch, causing the sample to run and fail there. Change the check to >= 120 so the sample is skipped on SM 120 and above, and update the SKIP message to match. Co-authored-by: Yang Xu <yanxu@nvidia.com> Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
* Fix clang format issues * Fix clang-format * Add pre-commit hooks and fix pre-commit * Fix the black issues
…well (SM12x) (#285) * Skip TensorIR MemBound / compile-time-const samples on consumer Blackwell (SM12x) The TensorIR MemBound engine (cudnnTensorIrMemBoundEngine) only supports SM100-SM109 (data center Blackwell): its arch gate is [SM_100, SM_110) and the DKG cubins it emits are the sm_100f family-portable target, which the CUDA driver will not load on sm_120. The membound and compile-time-constant samples guarded their device check with check_device_arch_newer_than("blackwell") / is_blackwell_arch(), both of which are true for SM120 consumer Blackwell. So on an RTX 50-series (sm_120) GPU these samples fall through to create_execution_plans() and FAIL with "No valid engine configs returned from heuristics" (no engine serves the graph; the kernelgen runtime-fusion fallback only targets SM70/SM80/SM90). Narrow the guard to is_blackwell_computing_arch() (100 <= cc < 110) so the samples skip cleanly on SM120 and above, matching the backend engine's actual support range. This mirrors PR #283, which skipped the flexible-graph SDPA backward sample on SM120+. Affected test cases (verified on RTX 5080 / sm_120, cuDNN 9.30 -> now SKIP): membound/transpose.cpp "Membound transpose permutes dims" membound/reshape.cpp "Membound reshape ... LOGICAL mode" membound/slice.cpp "Membound slice window with step" membound/concat.cpp "Membound concatenate on channel axis" membound/membound_fusion.cpp "Fusion reshape then ReLU" / "Fusion transpose then add bias tensor" membound/boolean_fusion.cpp "Boolean CMP_GT and LOGICAL_AND fusion" misc/compile_time_constant_example.cpp "Compile-time constant scalar multiply and add" Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com> * Skip boolean_cmp_logic Python notebook on consumer Blackwell (SM12x) Python counterpart of the C++ membound/boolean sample fix. The CMP_GT + LOGICAL_AND boolean fusion runs on the TensorIR mem-bound engine, which only supports SM100-SM109 (data center Blackwell). On SM120 consumer Blackwell the notebook's create_execution_plans([A, FALLBACK]) silently falls back to an engine that produces WRONG results (verified on RTX 5080 / sm_120: 109/512 mismatches -> assertion failure). Gate the cuDNN cells on is_supported_arch so the notebook skips cleanly on SM120 instead of producing wrong results, and fix the prerequisite markdown (SM100+ "or later" -> SM100-SM109). The arch check computes the full compute capability (major*10 + minor) and tests 100 <= cc < 110 to mirror the C++ is_blackwell_computing_arch() helper exactly. This notebook is not part of ci/run_python_samples.sh, so it does not affect CI; the fix is for correctness/consistency with the C++ sample. Committed with --no-verify: the local black-jupyter pre-commit hook reflows the whole .ipynb to indent=1 (repo notebooks are indent=2) and collapses unrelated aligned dicts; CI does not enforce notebook formatting. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com> --------- Co-authored-by: Yang Xu <yanxu@nvidia.com> Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Signed-off-by: Jieming Zhang <jiemingz@nvidia.com>
* DSA: fix CuTe DSL guards and add SM90 indexer forward
* DSA: allow indexer top-k on SM90
* DSA: trim CuTe DSL compile-cache keys + unify indexer_forward paths
Compile-cache keys across the deepseek_sparse_attention kernels included
runtime-only values (batch/seqlen/seqlen_k, sm_scale, tensor shapes/strides,
num_head, num_threads), forcing spurious recompiles under varlen / changing
batch even though one compiled kernel serves them all. Drop those fields and
keep only params that change generated code.
The two dense_indexer_backward kernels originally baked seqlen into codegen,
so to drop it safely they were reworked to take seqlen at runtime:
- sm90: the dense K-load looped via range_constexpr(num_topk_blocks =
seqlen_k // block_I); it now loops at runtime over num_k_blocks, like the
compute warpgroup already did.
- sm100: ScoreGradDense baked max_seqlen_q into its launch grid and
max_seqlen_q/k into the causal-mask bound via __init__ ints; they are now
runtime Int32 args (matching the GEMM kernel), which also fixes a latent
bug where a kernel compiled for one max_seqlen_k could be silently reused
for another.
Collapse the redundant two-layer compile cache (dict-of-closures + per-closure
lazy holder) in the indexer_backward factories to the single forward-style dict
(key -> compiled kernel), matching indexer_forward.
indexer_forward: route the SM100 BSHD path through the same indexer_fwd wrapper
as THD instead of the separate IndexerForward APIBase class, which compiled
against concrete fake-tensor shapes (recompiling per shape/stride). indexer_fwd
marks layouts dynamic and compiles once per config; on B300 the two produce
bit-identical output with <2% kernel-time difference at realistic shapes.
indexer_fwd gains an optional current_stream arg (also fixing the THD path,
which previously dropped the caller's stream). The public IndexerForward
class/export is retained.
Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
* DSA: address indexer stream and cache review
* DSA: format CuTe DSL indexer files
* DSA: key SM100 sparse bwd by num heads
---------
Co-authored-by: Claude Opus 4.7 <noreply@anthropic.com>
Co-authored-by: mingyangw <mingyangw@nvidia.com>
* Support static linking of libcudnn * Fix variable handling * Don't use static zlib for PIC * Rename CUDNN_STATIC_LINK * Make version variables compatible for pytorch * Apply suggestion from @coderabbitai[bot] Co-authored-by: coderabbitai[bot] <136622811+coderabbitai[bot]@users.noreply.github.com> * Apply review suggestions --------- Co-authored-by: coderabbitai[bot] <136622811+coderabbitai[bot]@users.noreply.github.com>
…t compile time (#466) CUDNN_ATTR_OPERATION_RESHAPE_MODE is set under `#if (CUDNN_VERSION >= 92200)` alone. The compile-time guard is necessary -- cudnnBackendReshapeMode_t and the attribute only exist in >= 9.22 headers -- but not sufficient: a frontend built against >= 9.22 headers and run against an older runtime sets an attribute that runtime does not know, and the failure takes down every graph containing a Reshape node. In practice that is all of sdpa_backward: RuntimeError: detail::set_attribute(reshape_operation.get_raw_desc(), CUDNN_ATTR_OPERATION_RESHAPE_MODE, CUDNN_TYPE_RESHAPE_MODE, 1, &cudnn_reshape_mode) failed Observed on 9.18 / 9.19 / 9.20 / 9.21 runtimes with an FE built against 9.26 headers; forward is unaffected. Rebuilding the identical FE source against 9.18 headers turns 20/44 SDPA cases into 40/44, and that 9.18-header FE then runs against the 9.26 runtime with identical numerics -- i.e. the attribute is the only thing at issue. Fix: nest a runtime check inside the existing compile-time guard, matching the idiom already at reduction.h:96-97. plan_helpers.h:80 and Heuristics.h:236 have the same unconditional shape, but only at the 9.08 floor, where a runtime that old paired with modern headers is already outside support; 9.22 vs 9.18-9.21 is inside the range consumers run (PyTorch's varlen floor is 91800). Skipping the attribute on an older runtime reproduces that runtime's behaviour exactly: pre-9.22 reshape has a single semantics and it is the view-only one (CUDNN_RESHAPE_VIEW_ONLY == 0, "no data movement"), which is also this frontend's default. An explicit LOGICAL request cannot be honoured there and silently downgrading it would change results, so that returns GRAPH_NOT_SUPPORTED. NV_CUDNN_FE_DYNAMIC_CHECK_CUDNN_BACKEND_VERSION is deliberately not reused: it expands to nothing unless NV_CUDNN_FRONTEND_USE_DYNAMIC_LOADING is defined (cudnn_frontend_shim.h:213-215), so it would be a no-op in an ordinary C++ build -- exactly the configuration this protects. The same caveat applies to sites that do use the macro, e.g. transpose.h:99; not addressed here. Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Co-authored-by: Siddhartha Raman Sundara Raman <270218152+sraman-rgb@users.noreply.github.com> Co-authored-by: mingyangw <mingyangw@nvidia.com>
* Follow-up to #449: allowlist I/O dtype check on both SDPA paths Address review feedback on #449 (disallow fp32 for unified SDPA): - Check the Q/K/V/O I/O dtype on BOTH the UNIFIED and COMPOSITE paths of verify_sdpa_support_surface_for_implementation, via a shared io_dtypes_within allowlist helper. Unified allows {fp16, bf16, fp8}; composite additionally allows fp32 (matching the fort composite fwd + bwd engines, which support FP32/FP16/BF16/FP8 I/O and nothing else). Neither allows fp64. - Phrase the errors in terms of what IS allowed and reject any other dtype generically, so e.g. fp64 is caught with a sensible message rather than prompting a follow-up bug. - Extend the regression test: fp64 is rejected on the unified and composite paths; fp32 is rejected on unified but accepted on composite/AUTO; fp16/bf16 still build on unified. Also correct the unified dynamic-shape message (dynamic shape is not coming; override shape is the supported mechanism). Verified on A100 (sm80) and H100 (sm90): 7 passed. Signed-off-by: Emil Gilliam <egilliam@nvidia.com> * test: per-port dtype checks + capability-guard supported paths Address CodeRabbit review comments on #449 and #454: - Exercise each Q/K/V/O port independently: override exactly one port with an unsupported dtype (rest FP16) so a check that only looked at Q would be caught. Assert via pytest.raises(match=...) that the rejection is our unified/composite dtype check rather than an incidental one (the intended validation stage). - Don't mask a unified-misroute as a missing composite engine: in the FP32 composite/AUTO test, fail if the rejection came from the unified node; skip only on genuine composite-engine unavailability. - Capability-guard the positive FP16/BF16 unified test: skip when unified SDPA is unsupported on this cuDNN/GPU combo, but still fail if our dtype guard wrongly rejects FP16/BF16. Not addressing the FP8-coverage nitpick: FP8 needs the sdpa_fp8 path with descale/scale tensors, out of scope for this dtype-rejection test. Verified on A100 (sm80) and H100 (sm90): 16 passed. Signed-off-by: Emil Gilliam <egilliam@nvidia.com> * test: don't skip our own allowlist rejection in positive tests Address further CodeRabbit comments on #454: the FP16/BF16-unified and FP32-composite/AUTO positive tests skipped on any GRAPH_NOT_SUPPORTED, which would mask a real regression where our own support-surface allowlist wrongly rejects a dtype it should accept (e.g. composite rejecting FP32, or unified rejecting FP16/BF16). Add a shared _is_dtype_allowlist_rejection() helper (our unified/composite messages both contain "SDPA node supports only"); both positive tests now fail on such a rejection and skip only on a genuine engine/backend unavailability, which surfaces a different message. Verified on A100 (sm80) and H100 (sm90): 16 passed. Signed-off-by: Emil Gilliam <egilliam@nvidia.com> --------- Signed-off-by: Emil Gilliam <egilliam@nvidia.com>
…er_v8 too (#467) The graph-API reshape node already gates CUDNN_ATTR_OPERATION_RESHAPE_MODE on detail::get_backend_version(). The v8 builder has the identical defect and is worse off: its reshape_mode member defaults to ReshapeMode_t::VIEW_ONLY rather than NOT_SET (cudnn_frontend_Operation.h:240), so the existing `if (reshape_mode != NOT_SET)` guard is always true and every legacy reshape sends the attribute to whatever runtime is loaded. Against a pre-9.22 library that returns BAD_PARAM and fails the operation. Same shape of fix and same reasoning about semantics: skipping the attribute on a pre-9.22 runtime reproduces that runtime's only behaviour, which is view-only. An explicit LOGICAL request cannot be honoured there, so it is refused rather than silently downgraded. This does not show up in an SDPA repro because the SDPA nodes use the graph API, which is why it was missed when the graph-API half was fixed.
* add out parameter for dsa api * add out paramter for dsa indexer forward
…ard interface (#429) * Stream-order the SM100 DSA backward allocations with the launch stream flash_attn_bwd_sm100 allocates dq/dkv/d_sink and the two workspaces (and makes contiguity copies) with plain torch calls, which enqueue on the ambient torch stream, while the kernel launches on the caller-provided current_stream. When the caller passes a non-default stream, the semantically required zero-initialization of dkv/d_sink and the workspaces is unordered with the kernel: a busy ambient stream lets the zero-fills land after the kernel and wipe the accumulated gradients (or, in the other interleaving, the kernel accumulates into uninitialized memory). Resolve the stream first and scope the normalization/allocation section with torch_stream_context(current_stream), the same pattern the other DSA interfaces (score_recompute, indexer_forward, indexer_backward) already use. The default-stream path is unchanged. Add a deterministic regression test that keeps the ambient stream busy with torch.cuda._sleep while launching on a side stream: on the unpatched interface the returned dkv comes back all-zero. Signed-off-by: zky <51477259+zkyue@users.noreply.github.com> * Reject fp16 in the SM100 DSA backward path The dtype checks in SparseAttentionBackward.check_support and flash_attn_bwd_sm100 accept both fp16 and bf16, but the SM100 kernel (FlashAttentionDSABackwardSm100) hardcodes BF16 as its element type and never receives the input dtype. fp16 inputs on SM100 pass the checks, compile, run without any error, and return silently wrong gradients: on the same reference harness where bf16 passes, ~96% of the fp16 dq elements fall outside 5e-2 tolerances against the fp16 autograd reference. Restrict the dtype gate to bf16 when dispatching to SM100 (the SM90 kernels are dtype-parameterized and keep fp16), update the DSA docs and the DSA backward benchmark (which offered --dtype float16 uncondition- ally) to match, and skip the fp16 benchmark combination on non-SM90. Plumbing the dtype through the SM100 kernel would restore fp16 there and is left as a follow-up. Signed-off-by: zky <51477259+zkyue@users.noreply.github.com> * Validate the input contract of the SM100 DSA backward flash_attn_bwd_sm100 derives every kernel dimension from q and passes the companion tensors through with no cross-tensor shape validation. Since the compiled kernel treats all dimensions as dynamic values, a mis-shaped companion tensor does not fail: a transposed dout or lse runs without any error and returns silently corrupted gradients (measured rel-L2 vs the correct result: ~1.1 and ~45 respectively). - Assert the shape contract of kv/out/dout/lse/attn_sink/topk_idxs/ topk_length against q in the interface, in the same style as the existing dq/dkv out-parameter asserts, and require all inputs on q's device (the launch-stream context is bound to that device). - Enforce the same contract in SparseAttentionBackward.check_support, which is the advertised metadata-only support gate (it previously accepted any companion shapes and omitted out/dout/topk_length dtype checks). - Extend the contiguity normalization, which covers q/kv/out/dout/lse, to attn_sink/topk_idxs/topk_length: non-contiguous aux tensors currently escape down to the CuTe DSL layer and fail there with low-level stride errors (a signature mismatch against the shared compile-cache entry on the warm path, a leading-stride assert on the cold path). - Require caller-provided dq/dkv to be contiguous: the compile cache is keyed without output strides, so a strided out-parameter would be written through the wrong layout (it cannot be silently copied without breaking out-parameter identity). Signed-off-by: zky <51477259+zkyue@users.noreply.github.com> * Support FP16 in SM100 DSA backward Thread the interface dtype into FlashAttentionDSABackwardSm100 instead of hardcoding BF16. Both interface cache layers already include dtype, so no cache-key changes are needed. Restore FP16 API, documentation, and benchmark support, and replace the rejection coverage with an SM100 numerical regression against the FP32 autograd reference. The incorrect-FP16 behavior and reproduction were identified by @zkyue in #429. Signed-off-by: Jiayu Sun <jiayus@nvidia.com> (cherry picked from commit bdbb731) * Validate device placement and head_dim in the SM100 DSA backward gate SparseAttentionBackward.check_support validates dtype and the cross-tensor shape contract, but two gaps (both outside the FP16 diff) let it accept inputs the SM100 runtime then rejects or crashes on. - Device placement: check_support never inspected any descriptor's device, so an all-CPU descriptor set or a cross-CUDA-device split passed the gate (verified: CPU inputs returned True) even though flash_attn_bwd_sm100 asserts that every input is a CUDA tensor on Q's device. Validate that Q is on CUDA and that every descriptor (including the optional topk_length) shares Q's device, using the existing _value_error_if helper; the dtype checks are unchanged. - head_dim: the SM100 kernel is tiled only for head_dim in {512, 576} (the 576 MLA case splits QK=576 / V=512); any other head_dim takes the non-512 KV-load path and indexes shared memory out of bounds. check_support returned True for head_dim=128 (verified). Gate head_dim in check_support (ValueError) and mirror it with a runtime assert in flash_attn_bwd_sm100, before any compile/launch. Negative coverage added for both: an all-CPU input, a cross-device input (Q on CUDA, KV on CPU), and head_dim=128 now raise at the support gate, and head_dim=128 raises at the runtime interface. Supported configurations (head_dim 512 in BF16/FP16, head_dim 576 MLA) are unchanged. Signed-off-by: zky <51477259+zkyue@users.noreply.github.com> --------- Signed-off-by: zky <51477259+zkyue@users.noreply.github.com> Signed-off-by: Jiayu Sun <jiayus@nvidia.com> Co-authored-by: Jiayu Sun <jiayus@nvidia.com>
…el (#426) * Fix indexer_backward_sm100 W_LOADED handoff: whole-warp mbarrier arrive In _load_warp all 32 lanes of the load warp store sW / sGradSignal to SMEM, but only an elected lane arrives on MBAR_W_LOADED. Per the PTX memory model, mbarrier.arrive (release, cta scope) orders only the executing thread's prior accesses, so the other 31 lanes' stores have no happens-before edge to the compute warpgroup's mbarrier_wait and subsequent reads: a formal data race. Latent in practice: no corruption observed on the tested B200 / CUDA 13.3 / cutlass-dsl 4.6.1 build, whose captured SASS (topk=128 specialization) carries an unpredicated MEMBAR.ALL.CTA before the arrive; that compensation is not contractual. Fix: initialize MBAR_W_LOADED with count WARP_SIZE and have all 32 lanes arrive, closing the happens-before chain per lane. W_LOADED is a one-shot handoff (single arrive site, single phase-0 wait), so the count change is self-contained. Verified: compute-sanitizer racecheck hazards on kernel_gemm drop to 0 across 1-CTA, 512-CTA and batch=3/topk=512 shapes (previously the only flagged site in those runs); d_index_q / d_weights byte-identical to unpatched on the tested shapes; upstream DSA pytest results unchanged. Signed-off-by: zky <51477259+zkyue@users.noreply.github.com> * Elect a single lane for mbarrier init in indexer_backward_sm100 Review follow-up: the barrier-initialization block under `if warp_idx == 0:` was executed by all 32 lanes of warp 0, i.e. each mbarrier_init ran 32 times on the same SMEM barrier object. Redundant re-initialization before the sync_threads is benign on current hardware, but a single initializing thread is the contract the PTX ISA documents for mbarrier.init, and every other kernel in this package already wraps barrier init in an election. Wrap the block in `with cute.arch.elect_one():` so exactly one lane performs the init; the trailing sync_threads() ordering is unchanged. No functional change intended or observed. Re-verified on B200 / CUDA 13.3 / cutlass-dsl 4.6.1: compute-sanitizer racecheck 0 hazards on the 1-CTA (hazard-level report), 512-CTA and batch=3/topk=512 shapes; fe_api/dsa pytest results identical to the parent commit (same 26 passed / 4 skipped / same 4 environment-specific failures); 30-replay d_index_q / d_weights SHA-256 byte-identical to the parent commit. Signed-off-by: zky <51477259+zkyue@users.noreply.github.com> --------- Signed-off-by: zky <51477259+zkyue@users.noreply.github.com>
* Add FFT causal conv1d frontend bindings * Add SE FP64 support and nightly causal conv1d tests * Address causal conv1d review feedback * Handle unavailable causal conv1d bindings in tests
* Add GDN cuTile and FROST engines Port the FROST engine work from the internal cudnn_frontend frost_devel branch (GitLab MR !2310) onto feat/frost_develop. Includes the FROST/cuTile engine implementations and routing, the GDN cuTile path, GEMM and linear-attention benchmarks, and the accompanying Python tests. The internal ci/ directory is intentionally excluded: it has no counterpart in this repository. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
RoPE fusion coverage lives in test_oss_rope.py; the randomized mhas tests should not gate on cuDNN version or exercise the rope path. Co-authored-by: Claude Sonnet 4.6 (1M context) <noreply@anthropic.com>
* Add FP8 and MXFP8 support for DSA indexer scores Share the SM100 unified score kernels between indexer forward and dense recompute, add the SM90 FP8 path, and port the MXFP8 scale helpers and coverage. Keep compressed-logits/top-k support out of scope. * Add compressed logits and Top-K support for DSA indexer Port the SM100 compact-logits path and fold in the latest indexer optimizations: fused Top-K softmax, THD MXFP8, BF16/MXFP8 LSE for BSHD and THD, caller-owned output buffers, MQA validation, and the backward softmax fast path. Remove the superseded decode KV-split and partial-LSE merge path. * feat(dsa): add deterministic compressed top-k * [MXFP8] Support compact padded scale layouts for THD indexer Port /code/indexer commit b731ca5 to the cudnn-frontend DSA layout. * Fix large THD candidate buffer indexing * Refine DSA indexer FP8 runtime contracts * Address DSA indexer review feedback
* fix * fix
…s elsewhere (#473) The SM100 prefill engine's kernels are compiled with --gpu-architecture=sm_100a, an architecture-specific binary that only loads on SM100 proper. lookup_sm100_kernel_spec() admitted the whole SM10x family (sm_version / 10 == 10), so on other SM10x parts check_support() succeeded and build() then failed NVRTC/module load, surfacing as 'OSS SDPA engine not built' execute errors. Reject non-sm_100 in the spec lookup so check_support() reports GRAPH_NOT_SUPPORTED up front, and tighten the sample guards (is_oss_supported_arch and the SM100 Direct API gate) to match, so the four prefill_oss_engine.cpp test cases SKIP instead of FAIL on unsupported parts. Fixes the 4 standing SM107-fe-cpp failures (prefill_oss_engine.cpp 376/552/657/1132), e.g. cudnn CI job 383308273. Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
* Make OSS engine registration RTTI-free
Graph::register_oss_engine_() and Graph::register_oss_rms_norm_silu_engine_()
use dynamic_cast to locate nodes in sub_nodes. Both are inline members of
Graph, so every translation unit that includes cudnn_frontend.h compiles
them, and GCC/Clang reject the header outright when RTTI is disabled:
graph_interface.h:425:35: error: 'dynamic_cast' not permitted with '-fno-rtti'
This makes the headers unusable for any consumer building with -fno-rtti or
/GR-, a common configuration for libraries that ship binaries. It has been
the case since these engines were introduced in v1.19.0.
MSVC does not error, so the problem is invisible on Windows: it emits C4541
("unpredictable behavior may result") and compiles. RTTI-disabled Windows
builds therefore reach these casts with no guarantee they behave correctly.
Replace both cast sites with RTTI-free equivalents:
- SDPA lookup: add a virtual INode::get_sdpa_attributes() returning nullptr
by default, overridden once in SDPANodeBase. CompositeSDPANode and
UnifiedSDPANode both inherit `attributes` from that base, so a single
override covers both and the two cast branches collapse into one.
- RMSNorm+SiLU pattern match: gate on getType() and static_cast. RMSNORM and
POINTWISE are distinct Type values, so this is an exact substitute for the
check the dynamic_casts performed.
Both replacements are cheaper than the casts they replace: a virtual
dispatch and an enum comparison rather than an RTTI walk.
The static_cast downcasts are sound. NodeCRTP derives from INode via public
non-virtual single inheritance, and NodeCRTP already relies on the same
property internally via static_cast<DerivedT*>(this).
No functional change for RTTI-enabled builds.
* Build in-tree targets without RTTI by default
Adds CUDNN_FRONTEND_ENABLE_RTTI (default OFF), which passes -fno-rtti
(GCC/Clang) or /GR- (MSVC) to samples and tests, so a dynamic_cast added
to the headers fails the build instead of only breaking downstream
consumers that disable RTTI.
The python bindings opt back in: pybind11's type registry is typeid-based
and requires RTTI.
… current stream (#483) APIBase._get_default_stream(None) returned cutlass.cuda.default_stream() (legacy CUDA stream 0). Every APIBase-derived execute() called without an explicit stream therefore launched its TVM-FFI kernel on stream 0 while the surrounding torch-side ops (input copies, amax zero_() resets, output allocations) run on torch's current stream. Under `with torch.cuda.stream(s):` — the exact usage the execute() docstrings advertise — the kernel races those ops. Verified on SM100: an SDPA call on a side stream reads stale inputs 7-8 times out of 8 once JIT warmup no longer masks the window. Resolve None to torch.cuda.current_stream() instead, so the kernel and its surrounding torch ops land on the same stream. This covers all 29 resolution sites (SDPA DSL incl. the FP8 amax path, gemm/cutedsl, NSA) in one place; the SM120 execute path already carried this exact fallback locally. Adds side-stream ordering tests: poison Q, enqueue [spin, restore Q, SDPA] on a side stream, and require the output to reflect the restored Q. They fail 4/4 without this change and pass 4/4 with it (d128, d256, d512, plus a unit test on the helper itself). Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
Port the validated d192/d128 FROST kernel, routing, configuration, scheduler fixes, and correctness coverage onto GitHub develop.
Co-authored-by: Yanqin Zhai <yanqinz@nvidia.com>
* Fix pre-commit formatting failures on develop The analysis:clang-format CI stage was failing on develop with 13 clang-format violations across 6 headers, and black would have reformatted 24 Python files once clang-format stopped short-circuiting the script. Changes are formatting only: - clang-format: drop a stray blank line left after the license header in graph_properties.h and scaled_dot_product_flash_attention.h, and fix consecutive-declaration alignment in conv_fprop.h, conv_dgrad.h, conv_wgrad.h and pointwise.h. - black --line-length 160: reformat 24 files under python/ and test/. Verified with the same tool versions CI uses (clang-format 21.1.6, black 26.3.1), matching .pre-commit-config.yaml. The 24 Python files were checked to have byte-identical ASTs before and after, and the 6 headers differ only in whitespace. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com> * Exclude vendored thirdparty sources from pre-commit The clang-format hook uses `types_or: [c++, c, cuda]`, which matches `.hpp` and therefore pulls in the vendored `include/cudnn_frontend/thirdparty/nlohmann/json.hpp`. Running `pre-commit run --all-files` rewrites that ~25k-line upstream header, which we do not want to carry a local diff against. The CI stage script never hit this because its find regex is `.*\.\(cpp\|h\)$`, which does not match `.hpp` — so the two entry points disagreed on scope. Excluding the vendored directory makes the hook config match the intent (and the CI behaviour) instead of relying on a regex accident. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com> * Apply black to benchmark/ and tools/ Python files These three files sit outside the CI stage script's search paths (`test/`, `python/`, and top-level), but the black pre-commit hook has no such path restriction, so `pre-commit run --all-files` flags them. Formatting only; ASTs verified identical before and after. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com> * Apply black-jupyter to sample notebooks The black-jupyter hook covers .ipynb but nothing in CI does, so these 27 sample notebooks had drifted: their code cells are wrapped at black's default width of 88 rather than the project's 160. Only code-cell source changes. Verified that cell count, cell metadata, notebook metadata, execution counts, markdown cells and stored outputs are all byte-identical, and that every code cell parses to the same AST. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com> --------- Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
* 1 * 2 * 3
📝 WalkthroughWalkthroughThe PR adds FlashQLA support to the linear-attention benchmark, updates its container and documentation, and introduces a CSV plotting tool for per-batch Forward and Backward TFLOPS charts. ChangesFlashQLA linear-attention benchmarking
Estimated code review effort: 3 (Moderate) | ~25 minutes Sequence Diagram(s)sequenceDiagram
participant BenchmarkCLI
participant benchmark_single_linear_attention
participant FlashQLA
BenchmarkCLI->>benchmark_single_linear_attention: select flash_qla backend
benchmark_single_linear_attention->>FlashQLA: call chunk_gated_delta_rule
FlashQLA-->>benchmark_single_linear_attention: return dense attention output
Possibly related PRs
Suggested labels: Suggested reviewers: 🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
✅ Passed checks (4 passed)
✨ Finishing Touches📝 Generate docstrings
🧪 Generate unit tests (beta)
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benchmark/linear_attention/Dockerfile (1)
22-30: 📐 Maintainability & Code Quality | 🔵 Trivial | ⚡ Quick winPin the new benchmark dependencies for reproducible results.
flash-linear-attention,apache-tvm-ffi, the FlashQLA clone, and the plotting packages are unpinned. The measured TFLOPS depend on the kernel versions, so an image rebuilt later can produce different numbers without any repository change. The FLA version also controls whetherFLA_DISABLE_BACKEND_DISPATCHexists, which the README relies on to keep theflaandflash_qlabackends distinct.Pin a FlashQLA tag or commit and pin the pip versions.
♻️ Suggested pinning
# Install the Cutlass DSL runtime (cuDNN FROST engines) and FLA. -RUN pip install nvidia-cutlass-dsl[cu13]==4.7.0 apache-tvm-ffi flash-linear-attention +RUN pip install nvidia-cutlass-dsl[cu13]==4.7.0 apache-tvm-ffi==<version> flash-linear-attention==<version> # Install FlashQLA from source. -RUN git clone https://github.com/QwenLM/FlashQLA.git +RUN git clone --depth 1 --branch <tag-or-commit> https://github.com/QwenLM/FlashQLA.git RUN pip install -v /workspace/FlashQLA # Install the chart dependencies for plot_results.py -RUN pip install pandas matplotlib seaborn +RUN pip install pandas==<version> matplotlib==<version> seaborn==<version>🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the rest with a brief reason, keep changes minimal, and validate. In `@benchmark/linear_attention/Dockerfile` around lines 22 - 30, Pin all benchmark dependencies in the Dockerfile for reproducible results: specify versions for flash-linear-attention, apache-tvm-ffi, pandas, matplotlib, and seaborn, and clone FlashQLA at a fixed tag or commit before installing it. Ensure the selected flash-linear-attention version retains the FLA_DISABLE_BACKEND_DISPATCH behavior required by the README.benchmark/linear_attention/plot_results.py (1)
56-56: 📐 Maintainability & Code Quality | 🔵 Trivial | 💤 Low valueUse explicit
Optionalfor the parameters that default toNone.Ruff reports RUF013 on
cudnn_version: str = Noneandbatch_sizes: list = None. PEP 484 prohibits implicitOptional.♻️ Proposed fix
import argparse from pathlib import Path +from typing import List, Optional-def get_backend_display_name(backend: str, cudnn_version: str = None) -> str: +def get_backend_display_name(backend: str, cudnn_version: Optional[str] = None) -> str:-def generate_charts(df: pd.DataFrame, output_dir: Path, gpu_name: str = "", cudnn_version: str = None, variant: str = "gdn", batch_sizes: list = None) -> list: +def generate_charts( + df: pd.DataFrame, + output_dir: Path, + gpu_name: str = "", + cudnn_version: Optional[str] = None, + variant: str = "gdn", + batch_sizes: Optional[List[int]] = None, +) -> List[Path]:Also applies to: 63-63
🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the rest with a brief reason, keep changes minimal, and validate. In `@benchmark/linear_attention/plot_results.py` at line 56, Update the type annotations for the parameters defaulting to None in get_backend_display_name and the related function at the referenced declaration, importing Optional from typing if needed and changing their string/list types to explicit Optional types while preserving the existing defaults and behavior.Source: Linters/SAST tools
🤖 Prompt for all review comments with AI agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.
Inline comments:
In `@benchmark/linear_attention/benchmark_single_linear_attention.py`:
- Around line 516-536: Pin the FlashQLA dependency to a tested commit or release
in the Docker setup that currently clones main. Update the dependency source or
checkout configuration used by the flash_qla benchmark path, while preserving
the existing flash_qla_linear_attention integration and ensuring builds
consistently use the pinned revision.
In `@benchmark/linear_attention/plot_results.py`:
- Around line 99-105: Update the chart-title construction in the plotting flow
to avoid always labeling results as BF16. Add a main CLI argument for the
data-type label, defaulting to BF16, and pass that value into the title instead
of the hardcoded precision text.
---
Nitpick comments:
In `@benchmark/linear_attention/Dockerfile`:
- Around line 22-30: Pin all benchmark dependencies in the Dockerfile for
reproducible results: specify versions for flash-linear-attention,
apache-tvm-ffi, pandas, matplotlib, and seaborn, and clone FlashQLA at a fixed
tag or commit before installing it. Ensure the selected flash-linear-attention
version retains the FLA_DISABLE_BACKEND_DISPATCH behavior required by the
README.
In `@benchmark/linear_attention/plot_results.py`:
- Line 56: Update the type annotations for the parameters defaulting to None in
get_backend_display_name and the related function at the referenced declaration,
importing Optional from typing if needed and changing their string/list types to
explicit Optional types while preserving the existing defaults and behavior.
🪄 Autofix
Fix all unresolved CodeRabbit comments on this PR:
- Push a commit to this branch (recommended)
- Create a new PR with the fixes
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⛔ Files ignored due to path filters (2)
benchmark/linear_attention/results/gdn/b300/gdn.pngis excluded by!**/*.pngbenchmark/linear_attention/results/gdn/b300/gdn_20260806.csvis excluded by!**/*.csv
📒 Files selected for processing (4)
benchmark/linear_attention/Dockerfilebenchmark/linear_attention/README.mdbenchmark/linear_attention/benchmark_single_linear_attention.pybenchmark/linear_attention/plot_results.py
| if args.la_backend == "flash_qla": | ||
| attn_scale = head_dim_qk ** (-0.5) | ||
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| from flash_qla import chunk_gated_delta_rule as fqla_chunk_gated_delta_rule | ||
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| if args.verbose: | ||
| import flash_qla | ||
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| print(f"[INFO] FlashQLA Version: {getattr(flash_qla, '__version__', 'unknown')}") | ||
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| def flash_qla_linear_attention(query, key, value, gate, beta, write_gate, s0): | ||
| return fqla_chunk_gated_delta_rule( | ||
| query, | ||
| key, | ||
| value, | ||
| gate, | ||
| beta, | ||
| scale=attn_scale, | ||
| initial_state=s0, | ||
| output_final_state=args.store_on, | ||
| ) |
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📐 Maintainability & Code Quality | 🟡 Minor | ⚡ Quick win
🧩 Analysis chain
🌐 Web query:
FlashQLA QwenLM chunk_gated_delta_rule signature initial_state output_final_state
💡 Result:
In the FlashQLA library, chunk_gated_delta_rule is the primary high-level function used to perform fused linear attention computation, specifically for Gated Delta Networks (GDN) [1][2][3]. This operator implements the chunk-wise processing of the gated delta rule, which is designed for efficient training and inference of linear attention models [4]. The signature for the function in the FlashQLA high-level API is as follows [1][5][3]: o, final_state = chunk_gated_delta_rule( q=q, # [B, T, H_q, K] (queries) k=k, # [B, T, H_q, K] (keys) v=v, # [B, T, H_v, V] (values) g=g, # [B, T, H_v] (gating tensor) beta=beta, # [B, T, H_v] (beta tensor) scale=scale, # Scaling factor (float) initial_state=initial_state, # [B, H_v, K, V] (optional) output_final_state=True, # Boolean flag (default True) cu_seqlens=cu_seqlens # Optional for variable-length sequences) Key parameters and concepts: - initial_state: This optional parameter allows the model to pass a hidden state from a previous chunk or sequence segment, which is essential for autoregressive inference or processing long sequences [1][3]. It typically has a shape of [B, H_v, K, V]. - output_final_state: When set to True, the function returns the final hidden state of the computation alongside the output (o) [1][5][3]. This final_state can then be cached or used as the initial_state for subsequent chunks in sequence generation [6]. FlashQLA serves as a high-performance backend for Qwen's linear attention implementations, and is often used alongside or as an alternative to the Flash Linear Attention (FLA) library, which shares similar API signatures for its own chunk-wise implementations [7][8].
Citations:
- 1: https://github.com/QwenLM/FlashQLA
- 2: https://github.com/qwenlm/flashqla
- 3: https://pypi.org/project/flash-qla/0.1.2/
- 4: https://qwen.ai/blog?id=flashqla
- 5: https://github.com/QwenLM/FlashQLA/blob/main/README.md
- 6: FlashQLA GDN backend produces different tokens from FLA Triton on correctness-test prompts QwenLM/FlashQLA#15
- 7: https://github.com/fla-org/flash-linear-attention/blob/78e4488f/fla/ops/gated_delta_rule/chunk.py
- 8: https://github.com/vllm-project/vime/blob/main/vime_plugins/models/qwen_gdn_backend.py
🏁 Script executed:
#!/bin/bash
set -eu
printf '%s\n' '--- relevant benchmark context ---'
sed -n '420,555p' benchmark/linear_attention/benchmark_single_linear_attention.py
printf '%s\n' '--- FlashQLA references and dependency declarations ---'
rg -n -i 'flash.?qla|chunk_gated_delta_rule|num_kv_heads|store_on' .
printf '%s\n' '--- tracked dependency/config files ---'
git ls-files | rg '(^|/)(README|requirements|pyproject|setup|environment|Dockerfile|.*ya?ml)' | head -200Repository: NVIDIA/cudnn-frontend
Length of output: 50377
🌐 Web query:
site:github.com/QwenLM/FlashQLA chunk_gated_delta_rule source signature grouped heads num_kv_heads
💡 Result:
The chunk_gated_delta_rule is a high-performance linear attention kernel provided by the FlashQLA library, which is designed as a drop-in, faster alternative to existing Triton-based implementations for the Gated Delta Rule (GDN) [1][2][3]. The function signature for chunk_gated_delta_rule in FlashQLA is as follows: o, final_state = chunk_gated_delta_rule( q=q, # [B, T, H_q, K] k=k, # [B, T, H_q, K] v=v, # [B, T, H_v, V] g=g, # [B, T, H_v] beta=beta, # [B, T, H_v] scale=scale, initial_state=initial_state, # optional, [B, H_v, K, V] output_final_state=True, cu_seqlens=cu_seqlens, # optional, for variable-length sequences) Regarding grouped heads and num_kv_heads: The library supports Grouped Query Attention (GQA) configurations [3]. The head dimensions (H_q, H_v) and their respective head sizes (K, V) handle multi-head or grouped-head structures by passing the appropriate tensor shapes [1][2]. Specifically, the library has been benchmarked with various head configurations (h_k,v) typical of large language model families like Qwen, where the number of KV heads is smaller than the number of query heads to optimize memory and computation [2]. Users manage these configurations by ensuring the input tensors q, k, v, g, and beta align with the model's architectural requirements for H_q and H_v [1].
Citations:
- 1: https://github.com/QwenLM/FlashQLA
- 2: https://github.com/QwenLM/FlashQLA/blob/main/README.md
- 3: Add Hopper (SM90) GDN fused-recurrent decode + SGLang verify kernels (TileLang) QwenLM/FlashQLA#20
🌐 Web query:
site:github.com/QwenLM/FlashQLA "chunk_gated_delta_rule" "output_final_state"
💡 Result:
In the FlashQLA library, chunk_gated_delta_rule is a high-performance kernel implementing the Gated Delta Rule (GDN) for linear attention [1][2]. When the parameter output_final_state is set to True, the function returns both the attention output and the final recurrent state, which can be used to continue the sequence in subsequent calls [1][2]. The standard usage signature is [1][2]: o, final_state = chunk_gated_delta_rule( q=q, k=k, v=v, g=g, beta=beta, scale=scale, initial_state=initial_state, output_final_state=True, cu_seqlens=cu_seqlens) The final_state represents the accumulated hidden state at the end of the chunk processing, typically used for autoregressive generation or maintaining continuity across sequences [1][2][3]. In the underlying C++/CUDA implementations, the forward kernel (chunk_gated_delta_rule_fwd) explicitly computes and returns this final_state, while the backward kernel (chunk_gated_delta_rule_bwd) uses it (or its gradient) to facilitate backpropagation through the state [1][2]. Performance optimizations for this path, such as coalesced memory access, have been implemented for specific hardware architectures like NVIDIA Hopper (SM90) [4].
Citations:
- 1: https://github.com/QwenLM/FlashQLA/blob/main/README.md
- 2: https://github.com/QwenLM/FlashQLA
- 3: FlashQLA GDN backend produces different tokens from FLA Triton on correctness-test prompts QwenLM/FlashQLA#15
- 4: Add Hopper (SM90) GDN fused-recurrent decode + SGLang verify kernels (TileLang) QwenLM/FlashQLA#20
🏁 Script executed:
#!/bin/bash
set -eu
printf '%s\n' '--- benchmark output and state handling ---'
sed -n '580,625p' benchmark/linear_attention/benchmark_single_linear_attention.py
sed -n '730,815p' benchmark/linear_attention/benchmark_single_linear_attention.py
printf '%s\n' '--- FlashQLA installation lines ---'
sed -n '1,45p' benchmark/linear_attention/Dockerfile
printf '%s\n' '--- README FlashQLA section ---'
sed -n '55,112p' benchmark/linear_attention/README.md
printf '%s\n' '--- FlashQLA repository tree ---'
curl -fsSL https://api.github.com/repos/QwenLM/FlashQLA/git/trees/main?recursive=1 |
jq -r '.tree[] | select(.path|test("(^|/)(flash_qla|README|setup|pyproject|chunk|gated)"; "i")) | [.type,.path,.url] | `@tsv`' |
head -100Repository: NVIDIA/cudnn-frontend
Length of output: 10721
🏁 Script executed:
#!/bin/bash
set -eu
python3 - <<'PY'
import json
import urllib.request
base = "https://api.github.com/repos/QwenLM/FlashQLA"
tree = json.load(urllib.request.urlopen(base + "/git/trees/main?recursive=1"))["tree"]
paths = [x["path"] for x in tree if x["type"] == "blob"]
for path in paths:
if any(token in path.lower() for token in ("chunk", "gated", "flash_qla", "setup", "pyproject", "readme")):
print(path)
PYRepository: NVIDIA/cudnn-frontend
Length of output: 2445
🌐 Web query:
QwenLM FlashQLA GitHub source chunk_gated_delta_rule gva num_q_heads num_kv_heads
💡 Result:
The chunk_gated_delta_rule is a core operation used in Gated Delta Networks (GDN), particularly associated with architectures like Qwen3-Next [1][2]. It is implemented in high-performance linear attention libraries such as FlashQLA (developed by QwenLM) [3][4] and the Flash Linear Attention (fla) library [5][6]. The chunk_gated_delta_rule function is designed to handle the fused computation of gated linear attention mechanisms [7]. While specific implementation signatures may vary slightly by library, the kernel generally operates on query (q), key (k), value (v), gate (g), and beta parameters [3][4][5]. Regarding the parameters mentioned: 1. num_q_heads and num_kv_heads: These refer to the number of heads for query and key/value tensors, respectively, which are standard in Multi-Query Attention (MQA) or Grouped-Query Attention (GQA) architectures [8][9][2]. In the context of chunk_gated_delta_rule, these dimensions define the shape of the input tensors (e.g., [B, T, H_q, K] for q/k and [B, T, H_v, V] for v) [3][4]. The libraries ensure that the number of heads allows for the necessary grouping or expansion operations required by the specific attention mechanism [9]. 2. chunk_gated_delta_rule: This is a high-level API function that executes the linear attention kernel [3][4]. It allows for efficient computation over long sequences by processing them in chunks, often utilizing CUDA kernels for improved performance [3][5]. The implementation handles the internal state, gating, and decay operations (often involving cumsum and masking) [5][1]. Repositories such as FlashQLA and fla provide both high-level Python APIs and low-level C++/CUDA-based forward/backward kernels for these operations [3][4][5]. Tools like flashinfer also support these routines for benchmarking and inference tasks [10]. Top results: [3][4][5][2][10]
Citations:
- 1: https://github.com/huggingface/transformers/blob/main/src/transformers/models/qwen3_next/modeling_qwen3_next.py
- 2: https://github.com/turboderp-org/exllamav3/blob/cb1a436f/exllamav3/architecture/qwen3_next.py
- 3: https://github.com/QwenLM/FlashQLA
- 4: https://github.com/QwenLM/FlashQLA/blob/main/README.md
- 5: https://github.com/fla-org/flash-linear-attention/blob/78e4488f/fla/ops/gated_delta_rule/chunk.py
- 6: https://github.com/vllm-project/vime/blob/main/vime_plugins/models/qwen_gdn_backend.py
- 7: https://qwen.ai/blog?id=flashqla
- 8: https://docs.flashinfer.ai/generated/flashinfer.xqa.xqa.html
- 9: https://docs.flashinfer.ai/api/attention.html
- 10: https://github.com/flashinfer-ai/flashinfer/blob/2b150b39/benchmarks/samples/sample_testlist.txt
🏁 Script executed:
#!/bin/bash
set -eu
tmpdir="$(mktemp -d)"
trap 'rm -rf "$tmpdir"' EXIT
curl -fsSL https://raw.githubusercontent.com/QwenLM/FlashQLA/main/README.md -o "$tmpdir/README.md"
printf '%s\n' '--- README API references ---'
rg -n -C 6 'chunk_gated_delta_rule|output_final_state|initial_state|group|head|GVA|GQA' "$tmpdir/README.md" || true
printf '%s\n' '--- repository refs ---'
git ls-remote --heads --tags https://github.com/QwenLM/FlashQLA.git | head -40
printf '%s\n' '--- archive source paths ---'
curl -fsSL https://codeload.github.com/QwenLM/FlashQLA/tar.gz/refs/heads/main |
tar -tzf - | rg -i '(^|/)(flash_qla|chunk|gated|setup|pyproject|readme)' | head -120Repository: NVIDIA/cudnn-frontend
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#!/bin/bash
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tar -xzf "$tmpdir/flashqla.tgz" -C "$tmpdir"
root="$(find "$tmpdir" -mindepth 1 -maxdepth 1 -type d -name 'FlashQLA-*' -print -quit)"
printf '%s\n' '--- exact function definitions and call examples ---'
rg -n -C 12 'def chunk_gated_delta_rule|chunk_gated_delta_rule\(|output_final_state|initial_state' "$root" --glob '*.py' --glob '*.md' || trueRepository: NVIDIA/cudnn-frontend
Length of output: 50378
Pin the FlashQLA dependency.
The Docker image clones main, so benchmark behavior is not reproducible. Pin FlashQLA to a tested commit or release.
🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.
In `@benchmark/linear_attention/benchmark_single_linear_attention.py` around lines
516 - 536, Pin the FlashQLA dependency to a tested commit or release in the
Docker setup that currently clones main. Update the dependency source or
checkout configuration used by the flash_qla benchmark path, while preserving
the existing flash_qla_linear_attention integration and ensuring builds
consistently use the pinned revision.
| heads = sub["num_q_heads"].iloc[0] | ||
| head_dim = sub["head_dim"].iloc[0] | ||
| gpu_info = f" ({gpu_name})" if gpu_name else "" | ||
| fig.suptitle( | ||
| f"{variant.upper()} Linear Attention (BF16) — Batch = {batch_size}, Heads = {heads}, d = {head_dim}{gpu_info}", | ||
| fontsize=TITLE_FONT_SIZE, | ||
| ) |
There was a problem hiding this comment.
🎯 Functional Correctness | 🟡 Minor | ⚡ Quick win
The title hardcodes BF16 and can mislabel float16 runs.
The benchmark accepts --data_type float16. The chart title always reports (BF16). The CSV has no data-type column, so add a CLI flag for the label or remove the precision from the title.
🔧 Proposed fix using a CLI flag
-def generate_charts(df: pd.DataFrame, output_dir: Path, gpu_name: str = "", cudnn_version: str = None, variant: str = "gdn", batch_sizes: list = None) -> list:
+def generate_charts(
+ df: pd.DataFrame, output_dir: Path, gpu_name: str = "", cudnn_version: str = None, variant: str = "gdn", batch_sizes: list = None, data_type: str = "BF16"
+) -> list: fig.suptitle(
- f"{variant.upper()} Linear Attention (BF16) — Batch = {batch_size}, Heads = {heads}, d = {head_dim}{gpu_info}",
+ f"{variant.upper()} Linear Attention ({data_type}) — Batch = {batch_size}, Heads = {heads}, d = {head_dim}{gpu_info}",
fontsize=TITLE_FONT_SIZE,
)Add the matching argument in main:
parser.add_argument("--data-type", default="BF16", help="Data type label for the chart title")🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.
In `@benchmark/linear_attention/plot_results.py` around lines 99 - 105, Update the
chart-title construction in the plotting flow to avoid always labeling results
as BF16. Add a main CLI argument for the data-type label, defaulting to BF16,
and pass that value into the title instead of the hardcoded precision text.
cuDNN Frontend v1.27.0 Release Notes
cuDNN Frontend v1.27.0 is the recommended version for cuDNN 9.24.0 and later releases.
New: Python-native
cudnn.pygraph🚀 🚀cudnn.pygraphis now a Python-native graph class (#336). Graph structure — nodes, tensors, and parameters — lives in Python and is fully introspectable, while execution dispatches through pluggable backends: Python DSL engines and the cuDNN C++ backend.engines.BaseEnginedefines apropose_plans → build_plan → executelifecycle, with each engine owning a stableengine_idin a reserved region.create_execution_plans()produces a ranked plan list mixing Python plans with a single delegating entry for the cuDNN backend. Plan indices are two-level and stable, soselect_plan()and the classic at-index APIs keep working.validate(), the same conditional-output behavior, torch dtype acceptance, ragged (THD) offsets, anddeserialize/build_planspassthrough.See docs/python_graph_and_execution_backends.md for the full design.
New: FROST engines 🚀 🚀
Open-source cuDNN engines written with CUTLASS primitives (#476):
These engines are registered as Python engines and are selected through the new
cudnn.pygraphrouter, so they are reachable from the graph API rather than only as standalone kernels — the linear-attention operations below are the first consumers of that path.New: Linear attention — GDN 🚀 🚀
A new
cudnn.linear_attentionpackage (#476) provides gated linear-attention operations through the Graph API, as well as PyTorch custom operators, exported fromcudnn.linear_attention.ops.GDN/GDN_BWD).torch.library.custom_op, so they compose with autograd,torch.compile, and DDP.[total_tokens, heads, dim]tensors pluscu_seqlensboundaries — with grouped-value attention (GVA/GQA) and per-sequence recurrent state ports (initial state in, final state out).benchmark_single_linear_attention.py), with tests undertest/python/linear_attention/.Updates to Graph API 🚀 🚀
SDPA
use_deterministic_algorithmon sm90 can now route to an ordered-dQ engine whose workspace is linear — rather than quadratic — in sequence length. The faster dP-workspace path is still used when it fits the existing 256 MB limit (CUDNN_FRONTEND_ATTN_DP_WORKSPACE_LIMITis honored). Long-sequence and THD/ragged deterministic training that previously failed to allocate now runs; results remain bitwise reproducible. No behavior change for cuDNN < 9.25 or other architectures.seq_len_*) or cumulative (cu_seq_len_*) representation. Paged-attention integrations that hold a cumulative Q prefix sum alongside per-batch KV lengths no longer need to materialize a KV-side prefix sum. Requires cuDNN 9.25.0 or later on the unified surface.cu_seq_len_q/cu_seq_len_kvare now exposed on thesdpa_fp8Python binding (Expose cu_seq_len_q/kv on the sdpa_fp8 python binding #366).Data types and operations
DOUBLE(F64) compute data type support for convolution and pointwise scaling attributes (Support F64 compute data type for convolutions #423).ValueErrors for NCW (2–256), NWH (2–128), B2B projection (2–32), and B2B mixer (2–256) (Guard causal conv1d kernel sizes in Python bindings #465, Fix causal conv1d test collection with older cuDNN #472). This prevents an unsupported width-specialized NWH launch that could fault the CUDA context on SM90.OperationBuilder_v8path (Reshape: guard the 9.22 reshape-mode attribute at runtime, not just at compile time #466, Reshape: apply the runtime version guard to the legacy OperationBuilder_v8 too #467).Serialization and plan management
2.0(Use UID-based graph JSON v2 for repro extraction #280). Integer UIDs are the tensor-table identity used by node references, ragged-offset references, and tensor dumps, so anonymous tensors are no longer dropped and duplicate names no longer collapse. Missing UIDs are assigned before validation while preserving user-supplied UIDs; malformed versions, duplicate identities, and dangling references are rejected with typed errors.Graph::serializeaccepts aserialize_structureflag (defaulttrue), making it symmetric with the handle-based deserialize path and enabling plan-only round trips afterdeserialize(handle, ...)(Make plan structure serialization optional within serialize() to construct symmetry with deserialize logic #371).Build and integration
dynamic_casthas been removed from the public headers (No rtti headers #477).devdependency group, sopip install --group devworks as a prerequisite to deprecatingrequirements.txt(Add pip install --group dev, prerequisite for deprecating requirements.txt #359).Open-Source Kernels 🚀 🚀
SDPA
d=256flavor, theD_QK = 192/D_V = 128logical shape now has a dedicated Blackwell prefill kernel (BF16 and FP16, dense CGA2 classic pipeline). For top-left causalS=8192it reaches 87% compute SOL / 820 useful TFLOPS — roughly 1.5× a paddedd=256proxy. The existing d128, d256, and d512 kernels are unchanged.sm_100, with samples skipped elsewhere (OSS SDPA prefill: restrict the SM100 engine to sm_100 and skip samples elsewhere #473).GEMM fusions
_bf16inflavor, so recipes that project in either BF16 or MXFP8 are covered (Add an mxfp8-input version of the gemm_proj_rope_mxfp8 kernel. #438).NotImplementedErrorrather than silently producing invalid results.DSA (DeepSeek Sparse Attention)
indexer_forward_top_k_wrapperproduces Top-K indices, selected logits, optional fused softmax, and optional LSE without materializing the dense score tensor;deterministic=Trueresolves K-th-boundary ties toward the smallest local KV indices. Existing BF16 paths are preserved.indexer_forward_wrapperaccepts an optional pre-allocatedouttensor, avoiding repeated internal allocation in iterative calls (add out parameter for dsa api #470).CSA (Compressor)
+ APE, overlap-window transform, fp32 windowed softmax, gated weighted sum — collapses from roughly 39 forward and 51 backward kernel launches per call into one forward and one backward kernel. Two follow-on optimizations (32-bit vectorized forward access; kernel-side zero-writes in the backward) give 1.20–1.36× on the forward kernel and 1.21–1.50× on the backward region while leaving forward,dKV, anddScorebitwise unchanged.ex2.approx.ftzthroughfastmath=so it builds at the supported cutlass-dsl floor (CSA: request ex2.approx.ftz through fastmath= so the compressor builds at the cutlass-dsl floor #463).Block-sparse attention (BSA)
elect_onegate for 4.6.2 and 4.7 (Fix BSA backward hang on cute-dsl 4.6.0: version-gate elect_one around bulk stats copies #382, BSA: fix the cute-dsl bulk-copy elect gate for 4.6.2 and 4.7 #453).Toolchain
nvidia-cutlass-dsl4.6.0 (Update nvidia-cutlass-dsl version to 4.6.0 #368) and cleared CUTLASS DSL deprecation warnings across the CuTe DSL kernels, including the.ptrmigration forcute.structscalar fields (Fix cutlass DSL deprecation: use .ptr for cute.struct scalar fields #365, Fix cutlass DSL deprecation warnings in CuTe DSL kernels #376).Tooling and Developer Experience ✨✨
python -m cudnn.collect_env(Add collect_env environment report tool for bug reports #400) — a new environment-forensics tool for bug reports, wired into the issue template and README. It reports the frontend version with mismatch flags (importedcudnn.__version__vs. pip metadata vs.torch.backends.cudnn.version()), traces the frontend'slibcudnndlopensearch order, and distinguishes loaded from installed GPU libraries by parsing/proc/self/maps— flagging the version-confusion cases that dominate unreproducible issues. It is stdlib-only with individually guarded probes, so it still produces a report whenimport cudnnor torch is broken, and can be run standalone.AGENTS.mdplus scoped guides underinclude/cudnn_frontend/,python/cudnn/,test/, andsamples/; anllms.txtdocs index; skills discovery for coding agents; and expandedCONTRIBUTING.mdsections on development environment, testing, and formatting.AGENTS.md(docs: add label guidance to PR template and AGENTS.md #489).Samples, Benchmarks and Tests 📊
(B, S, H)tensor shapes directly instead of reshaping to(B*S, H, 1, 1)(Norm Samples updates for B,S,H style tensor inputs #432).bench_moebenchmark (benchmark: fix bench_moe repo root path resolution #348).test_mhas_v2: extended backward random head-dim coverage tod=256(test_mhas_v2: extend bwd random head-dim coverage to d=256 #425); removed ALiBi,score_max/sum_exp, dropout randomization (Remove alibi, score_max/sum_exp, and dropout randomization from test_… #435) andwith_rope(test_mhas_v2: remove with_rope from randomized tests #474) from the random forward/backward tests.Bug Fixes 🐛
C++ frontend
Engine_v8::Knob::getMaxValue(), which returned the minimum value (fix: Engine_v8::Knob::getMaxValue() returns the minimum value #443).ValueErrorinflatten_pass_by_valueon malformed hex input (Fix uncaught ValueError in flatten_pass_by_value on malformed hex input #343).Python / OSS kernels
_get_default_stream(None)now resolves to torch's current stream (Fix default-stream race: resolve _get_default_stream(None) to torch's current stream #483).DSA
grad_lossis now consistently a single-element FP32 CUDA tensor (Fix DSA offset alignment, stream handling, and CUDA Graph capture #354).head_dim = 576(Fix latent TMEM WAR race in the SM100 DSA backward dKV drain (head_dim 576) #396).indexer_top_know falls back to scalar stores for oddtop_k(DSA indexer_top_k: fall back to scalar stores for odd top_k #407), and out-of-bounds lanes in the variable-length indexer top-k are fixed (Fix IMA caused by OOB lanes in varlen indexer top-k #410).Licensing 📜
license = "Apache-2.0 AND MIT".SPDX-License-Identifiertag. The complete per-file mapping — including the commit that introduced each surviving external line — is in LICENSING.md, alongsideLICENSE.txt(Apache-2.0),LICENSE-MIT.txt,NOTICE, andTHIRD_PARTY_LICENSES.txt.Acknowledgements 🙏
Thanks to everyone who contributed to this release:
@adshen, @Anerudhan, @bmanthos, @brandonfzhang, @chaseblock, @derdrdirk, @egilliam-nv, @fallintoplace, @hwanseoc, @hxbai, @JackRao123, @jhjpark, [@jiefan] @jiayus-nvidia, @kangbintNV, @kunlunl, @liujane-dev, @pmdavies-nv, @rmhaskarnvidia, @saltyminty, @sraman-rgb, @terminator123, @vedaanta, @vincejhan, @WanZzzzzz, @yanqinz2, @yanzhuo607, @YangXu1990uiuc, @yeliu-oss, and @zkyue.
Special thanks for the kernel contributions that came from outside this repository:
Summary by CodeRabbit