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Fix IMA caused by OOB lanes in varlen indexer top-k - #410

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Anerudhan merged 1 commit into
NVIDIA:developfrom
hxbai:fix/indexer-topk-varlen-oob-predicate
Jul 28, 2026
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Fix IMA caused by OOB lanes in varlen indexer top-k#410
Anerudhan merged 1 commit into
NVIDIA:developfrom
hxbai:fix/indexer-topk-varlen-oob-predicate

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@hxbai

@hxbai hxbai commented Jul 20, 2026

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Before submitting

  • I agree to license this contribution under the terms of LICENSE.txt.
  • I ran pre-commit run and committed any formatting changes.

Affected area

  • FE OSS kernels or CuTeDSL

Summary

Fix the varlen indexer top-k kernel so that out-of-bounds lanes from predicated vector loads do not participate in radix histogram construction or candidate collection.

The change applies the existing vector-lane bounds predicate during:

  • coarse histogram construction;
  • direct candidate collection;
  • initial refinement histogram and candidate spill.

A regression test covers rows where the valid input prefix contains fewer finite values than top_k, making the top-k threshold -inf.

Why

The kernel uses predicated vector loads and fills out-of-bounds register lanes with -inf. However, those lanes were still counted in the radix histogram and could subsequently be collected as top-k candidates.

When the real top-k threshold was also -inf, the kernel could not distinguish valid in-range -inf values from the synthetic OOB values. This produced thousands of invalid candidates, overflowed the per-row extra buffer, and resulted in an illegal memory access.

Filtering candidates by their logical input index fixes the issue while preserving valid top-k semantics for real in-range -inf values.

Related issues

None.

API and compatibility impact

None. There are no public API or input-contract changes.

The kernel now excludes internal OOB vector lanes from top-k selection. Valid in-range values, including -inf, retain their existing top-k semantics.

Testing

Tested on an NVIDIA B200 (SM100) with CUDA launch blocking enabled.

  • python -m pytest -q --tb=short fe_api/dsa/test_DSA_indexer_top_k.py
    • 5 passed
  • Replayed the original failing input:
    • shape: (633, 768)
    • dtype: float32
    • seq_lens=633
    • top_k=512
    • completed without IMA
  • Replayed the original failing input for 100 consecutive iterations:
    • all iterations completed without IMA
  • git diff --check
    • passed

Summary by CodeRabbit

  • Bug Fixes

    • Corrected top-k selection to ignore padded vector lanes during histogram processing and index collection.
    • Prevented out-of-range padded values from influencing top-k results, including inputs containing negative infinity.
  • Tests

    • Added coverage verifying returned indices remain within valid sequence bounds and match expected top-k values.

Signed-off-by: Hongxiao Bai <hongxiaob@nvidia.com>
@coderabbitai

coderabbitai Bot commented Jul 20, 2026

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Review Change Stack

📝 Walkthrough

Walkthrough

The varlen top-k kernel now excludes vector-tail padding from histogram construction, index collection, and refinement. A CUDA regression test verifies that negative-infinity padding does not affect returned indices or selected values.

Changes

Varlen top-k padding handling

Layer / File(s) Summary
Guard padded lanes in top-k processing
python/cudnn/deepseek_sparse_attention/indexer_top_k/indexer_top_k_varlen_util.py
Stage 1 histogram updates, coarse index emission, and refinement operations now run only when each lane’s relative index is below aligned_size.
Validate negative-infinity padding behavior
test/python/fe_api/dsa/test_DSA_indexer_top_k.py
Adds a CUDA-gated test that checks returned indices remain in range and selected values match torch.topk over real input columns.

Estimated code review effort: 3 (Moderate) | ~20 minutes

Suggested reviewers: anerudhan

🚥 Pre-merge checks | ✅ 4 | ❌ 1

❌ Failed checks (1 warning)

Check name Status Explanation Resolution
Docstring Coverage ⚠️ Warning Docstring coverage is 66.67% which is insufficient. The required threshold is 80.00%. Write docstrings for the functions missing them to satisfy the coverage threshold.
✅ Passed checks (4 passed)
Check name Status Explanation
Linked Issues check ✅ Passed Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check ✅ Passed Check skipped because no linked issues were found for this pull request.
Title check ✅ Passed The title clearly matches the main fix: preventing illegal memory access from out-of-bounds lanes in varlen top-k.
Description check ✅ Passed The description follows the template well and includes the required sections, rationale, compatibility impact, and testing details.
✨ Finishing Touches
🧪 Generate unit tests (beta)
  • Create PR with unit tests

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@hxbai
hxbai marked this pull request as ready for review July 20, 2026 09:45
@Anerudhan

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@Anerudhan Anerudhan added cat-bug Reports of incorrect behavior, crashes, regressions, or unexpected results. orig-nv-eng Reported or requested by NVIDIA engineering. mod-cutedsl CuTeDSL kernels, generated kernels, examples, or related integration work. labels Jul 20, 2026
@Anerudhan Anerudhan added this to the Frontend 1.27.0 milestone Jul 20, 2026
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🚀 Running mirror pipeline

Branch: cudnn-gh/pr-410-782c445
Pipeline: 59853073

@JackRao123

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We independently hit this exact bug in production and can confirm the diagnosis — thanks for fixing it.

Our data point: a GLM-5.2 context-parallel (CP32) training run on B200s crashed with Xid 43 (illegal memory access) mid-forward_backward, roughly once per several hours of long-context training. CUDA_LAUNCH_BLOCKING=1 attributes the fault to cute_dsl_topk_wrapper; the captured input (a (862, 4310) fp32 score chunk, top_k=2048) reproduces the crash deterministically in a fresh process — same call, same iteration, on both B200 (SM100) and B300 (SM103); compute-sanitizer shows the invalid 2-byte shared writes from the candidate-buffer overflow.

One extra trigger route worth noting alongside yours: our rows had plenty of finite values — the threshold landed in the -inf bin because to_coarse_key converts fp32 scores to fp16 first, so every score below −65504 collapses into the fp16 -inf bin with the phantom lanes. (2242 real + ~4072 phantom candidates vs 512 + 4310 buffer capacity in the large-occupancy compile.) Your fix covers both routes since it filters by logical index.

We verified an equivalent patch on our side: previously-crashing inputs pass with exact torch.topk parity, sanitizer-clean, across B200 and B300. Happy to contribute our regression test (which includes the hard-crash variant) if useful, but whichever lands first works for us.

@Anerudhan
Anerudhan merged commit 32fe74d into NVIDIA:develop Jul 28, 2026
1 check passed
Anerudhan added a commit to Anerudhan/cudnn-frontend that referenced this pull request Jul 29, 2026
…y MIT)

Rebased onto current develop (4f75b1f). Relicenses NVIDIA-authored code from
MIT to Apache-2.0 using the exact NVIDIA OSS SPDX header, while keeping under
MIT every file that carries non-NVIDIA contributions, so no third party's code
is relicensed without consent.

License assignment (per-file SPDX tag on every source file):
- Apache-2.0: 515 files authored solely by NVIDIA (incl. the new Rubin/BF16
  grouped GEMM kernels and gemm_proj_rope_mxfp8 variants).
- MIT (67): files with surviving lines from external contributors in the
  issue NVIDIA#431 sign-off list, determined by git blame on develop.
- MIT (29): FlashAttention/QuACK-derived files carrying external authors'
  copyright; pinned to MIT so the Apache-2.0 root does not absorb them.

New since the previous revision of this PR (develop 3a9ed3f -> 4f75b1f):
- 26 new files headered; 63 modified files re-analyzed.
- Two new external contributors, adding 4 files to the MIT set:
  DrDirk (NVIDIA#423) -> conv_dgrad.h, conv_fprop.h, conv_wgrad.h
  Hongxiao (NVIDIA#410) -> test/python/fe_api/dsa/test_DSA_indexer_top_k.py
  Both must be added to the issue NVIDIA#431 consent list.
- rmhaskar (NVIDIA#432) verified NVIDIA-affiliated; Chase Block now commits from an
  NVIDIA address. Neither adds MIT files.
- PR NVIDIA#434 removed the Jerry Chen personal copyright from bwd_barriers.py;
  6 other DSA files still carry it and remain Category 2.

Licensing files: LICENSE.txt (Apache-2.0), LICENSE-MIT.txt, LICENSING.md
(dual-license manifest with per-file introducing-commit links),
THIRD_PARTY_LICENSES.txt, NOTICE, pyproject ('Apache-2.0 AND MIT'), README.

Every change is comment/header-only; all Python compiles.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Anerudhan added a commit to Anerudhan/cudnn-frontend that referenced this pull request Jul 30, 2026
…MIT)

Rebased onto current develop (b950af1). Relicenses NVIDIA-authored code from
MIT to Apache-2.0 using the exact NVIDIA OSS SPDX header, keeping under MIT
only files that still carry contributions from external contributors whose
permission has not been established.

License assignment (per-file SPDX tag on every source file):
- Apache-2.0: 541 files
- MIT (50): surviving lines from external contributors, consent pending
- MIT (29): FlashAttention/QuACK-derived files carrying external authors'
  copyright

Cleared, freeing 16 files to Apache-2.0:
- Written consent on issue NVIDIA#431 (10): take-cheeze, fallintoplace, zianglih,
  JackRao123, zkyue, Hyaloid, haowen-han, junaire, szluyu99, dimitar-asenov.
- NVIDIA employment (2), commits under personal email addresses:
  HollowMan6, and hxbai (Hongxiao Bai, PR NVIDIA#410) -- frees
  .../indexer_top_k/indexer_top_k_varlen_util.py and
  test/python/fe_api/dsa/test_DSA_indexer_top_k.py.
Files touched by both a cleared and a still-pending contributor remain MIT.

PR NVIDIA#427 (CSA fused Compressor kernels ported from Megatron-LM, author @zkyue
who consented): its 13 files had no license header at all; they now carry the
NVIDIA Apache-2.0 SPDX header. Megatron-LM added to THIRD_PARTY_LICENSES.txt
as an NVIDIA Apache-2.0 provenance note.

Still pending (7): ConnorBaker, DrDirk, EmilienM, jyknight, sbcd90, valgur,
and co-author Benjamin Leff.

Every change is comment/header-only; all Python compiles.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Anerudhan added a commit that referenced this pull request Jul 30, 2026
…MIT) (#408)

Rebased onto current develop (b950af1). Relicenses NVIDIA-authored code from
MIT to Apache-2.0 using the exact NVIDIA OSS SPDX header, keeping under MIT
only files that still carry contributions from external contributors whose
permission has not been established.

License assignment (per-file SPDX tag on every source file):
- Apache-2.0: 541 files
- MIT (50): surviving lines from external contributors, consent pending
- MIT (29): FlashAttention/QuACK-derived files carrying external authors'
  copyright

Cleared, freeing 16 files to Apache-2.0:
- Written consent on issue #431 (10): take-cheeze, fallintoplace, zianglih,
  JackRao123, zkyue, Hyaloid, haowen-han, junaire, szluyu99, dimitar-asenov.
- NVIDIA employment (2), commits under personal email addresses:
  HollowMan6, and hxbai (Hongxiao Bai, PR #410) -- frees
  .../indexer_top_k/indexer_top_k_varlen_util.py and
  test/python/fe_api/dsa/test_DSA_indexer_top_k.py.
Files touched by both a cleared and a still-pending contributor remain MIT.

PR #427 (CSA fused Compressor kernels ported from Megatron-LM, author @zkyue
who consented): its 13 files had no license header at all; they now carry the
NVIDIA Apache-2.0 SPDX header. Megatron-LM added to THIRD_PARTY_LICENSES.txt
as an NVIDIA Apache-2.0 provenance note.

Still pending (7): ConnorBaker, DrDirk, EmilienM, jyknight, sbcd90, valgur,
and co-author Benjamin Leff.

Every change is comment/header-only; all Python compiles.

Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
@Anerudhan Anerudhan mentioned this pull request Aug 6, 2026
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cat-bug Reports of incorrect behavior, crashes, regressions, or unexpected results. mod-cutedsl CuTeDSL kernels, generated kernels, examples, or related integration work. orig-nv-eng Reported or requested by NVIDIA engineering.

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