feat(rocjitsu): cdna5 OOB behavior implementation by lua1235 · Pull Request #10362 · ROCm/rocm-systems

lua1235 · 2026-08-18T21:45:30Z

Motivation

Implement OOB memory access behavior for gfx1250/cdna5. Lay groundwork for other architectures.

Technical Details

Implemented missing gfx1250’s per-component VBUFFER OOB behavior.
Model CDNA5 descriptor bounds, scaled stride, OOB_SELECT, and 45-bit offset rules.
Implement ordinary aligned, unswizzled TYPE=0 semantics: each dword is checked independently, OOB load components return zero, OOB store components are dropped, atomics remain all-or-nothing, and valid lanes retain coalesced cache traffic. Swizzle, alignment modes/MEMVIOL, and resource-TYPE validation remain follow-ups.

Issue Tracking

N/A

Test Plan

Added new tests. Ran tests.

Test Result

Tests pass.

Submission Checklist

Look over the contributing guidelines at https://github.com/ROCm/rocm-systems/blob/develop/CONTRIBUTING.md.

therock-pr-bot · 2026-08-18T21:46:39Z

❌ PR Check — Action Required

Check	Status	Details
📝 PR Description	❌ Fail	Error: PR description must reference a JIRA ID, ISSUE ID, or a GitHub closing keyword. Expected: include a `JIRA ID` / `ISSUE ID` line (separator `:` or `-`, or omitted; value may be a JIRA key, a number with/without `#`, or a link), OR a closing keyword + issue reference. Accepted examples: • `JIRA ID : TESTAUTO-6039` • `JIRA ID - #330` • `JIRA ID #330` • `JIRA ID` (on separate line) `ROCM-25757` • `ISSUE ID : TESTUTO-3334` • `ISSUE ID #3334` • `ISSUE ID - TESTAUTO-3433` • `ISSUE ID` (on separate line) `AIRUNTIME-2352` • `ISSUE ID : https://github.com/<org_name>/<repo_name>/issues/1234` • `Closes #10` • `Fixes octo-org/octo-repo#100` • `Resolves: #123` • `#123` • `https://github.com/<org_name>/<repo_name>/issues/123` Current: no valid JIRA/ISSUE/closing-keyword reference found
⛔ Forbidden Files	✅ Pass	—
🧪 Unit Test	✅ Pass	—
🔎 pre-commit	✅ Pass	—
🚫 Draft PR	🔜 To Be Enabled	—
🚩 Feature Flag	🔜 To Be Enabled	—
📊 Code Coverage	🔜 To Be Enabled	—

⚠️ 1 policy check(s) failed. Please address the issues above before this PR can be Reviewed.

🚫 Please fix the failed policies

❌ PR Description

The Not ready to Review label was added to this PR. Once all policies pass, the label is removed automatically.

📖 Need help? See the Policy FAQ for details on every check and how to fix failures.

🙋 Wish to Override Policy?

therock-pr-bot · 2026-08-18T21:46:40Z

🚫 Please fix the failed policies before requesting reviews.

The following policy checks failed:

❌ PR Description

The Not ready to Review label has been added to this PR.
Once all policies pass, the label will be removed automatically.

atgutier

[MAJOR] emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.cpp:162 —
Descriptor bit 28 is part of OOB_SELECT, not a swizzle-enable flag

Reasoning: CDNA5 encodes OOB_SELECT as the two-bit field [29:28]:

00: index-and-offset bounds
01: index-only bounds
10: OOB only when NUM_RECORDS == 0
11: complete byte-extent bounds

The PR instead decodes bit 28 as swizzle_enabled and bit 29 as a Boolean oob_select. Consequently,
descriptors using modes 01 or 11 take the swizzle_enabled branch at lines 285–289 and bypass bounds
checking entirely. The other two modes are also conflated into one optional stride check.

Evidence: With mode 01, NUM_RECORDS == 0, and index zero, the access must be OOB. The implementation
sees bit 28, treats the descriptor as swizzled, and leaves the lane active. tests/
shared_infra_test.cpp:4707 currently codifies this incorrect interpretation by setting bit 28 and
expecting bounds to be disabled.

Suggested fix: Decode (srd3 >> 28) & 0x3 as a four-value OOB_SELECT mode, remove the bit-28 swizzle
bypass, and implement each mode explicitly. Add tests for all four encodings, especially zero
records in modes 01 and 10.

Confidence: high.

[MAJOR] emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.cpp:292 —
SOFFSET incorrectly participates in both bounds comparisons

Reasoning: The scalar offset affects the final effective address but is excluded from buffer bounds
checking. Lines 292–300 add soffset_val to both record_offset and total_offset, so increasing
SOFFSET can incorrectly turn a valid access into an OOB load/store.

For example, with a raw 16-byte resource, zero vector/immediate offset, and SOFFSET == 16, the
access should remain valid and target base + 16. The current comparison tests offset 16 against the
resource bound and masks even a B32 access.

Evidence: The public compiler contract distinguishes the checked offset—split into vector and
immediate fields—from SOFFSET, which is explicitly excluded from bounds checking. This also matches
the established rocjitsu buffer-address convention in shared/addr_calc_buffer.h:68–71. The new test
at tests/shared_infra_test.cpp:4622 assumes the opposite behavior.

Suggested fix: Remove soffset_val from record_offset and total_offset; retain it only in final
address generation. Replace the current SOFFSET test with one proving that changing SOFFSET changes
the address without changing the OOB result.

Confidence: high.

kuhar

Just one comment

lua1235 · 2026-08-19T15:15:32Z

@atgutier

[MAJOR] emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.cpp:162 — Descriptor bit 28 is part of OOB_SELECT, not a swizzle-enable flag

Reasoning: CDNA5 encodes OOB_SELECT as the two-bit field [29:28]:

00: index-and-offset bounds

01: index-only bounds

10: OOB only when NUM_RECORDS == 0

11: complete byte-extent bounds

The PR instead decodes bit 28 as swizzle_enabled and bit 29 as a Boolean oob_select. Consequently, descriptors using modes 01 or 11 take the swizzle_enabled branch at lines 285–289 and bypass bounds checking entirely. The other two modes are also conflated into one optional stride check.

Evidence: With mode 01, NUM_RECORDS == 0, and index zero, the access must be OOB. The implementation sees bit 28, treats the descriptor as swizzled, and leaves the lane active. tests/ shared_infra_test.cpp:4707 currently codifies this incorrect interpretation by setting bit 28 and expecting bounds to be disabled.

Suggested fix: Decode (srd3 >> 28) & 0x3 as a four-value OOB_SELECT mode, remove the bit-28 swizzle bypass, and implement each mode explicitly. Add tests for all four encodings, especially zero records in modes 01 and 10.

Confidence: high.

The two bit layout described above is actually the RDNA4 layout specifically. CDNA5 ISA defines SRD bit 124 as swizzle_enable and Bit 125 as a one-bit OOB_SELECT. See section 9.4.1 (Range Checking) for CDNA5 OOB semantics and 9.6 (Buffer Resource) for the bit layout. https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/instruction-set-architectures/amd-instinct-cdna5-instruction-set-architecture.pdf

[MAJOR] emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.cpp:292 — SOFFSET incorrectly participates in both bounds comparisons

Reasoning: The scalar offset affects the final effective address but is excluded from buffer bounds checking. Lines 292–300 add soffset_val to both record_offset and total_offset, so increasing SOFFSET can incorrectly turn a valid access into an OOB load/store.

For example, with a raw 16-byte resource, zero vector/immediate offset, and SOFFSET == 16, the access should remain valid and target base + 16. The current comparison tests offset 16 against the resource bound and masks even a B32 access.

Evidence: The public compiler contract distinguishes the checked offset—split into vector and immediate fields—from SOFFSET, which is explicitly excluded from bounds checking. This also matches the established rocjitsu buffer-address convention in shared/addr_calc_buffer.h:68–71. The new test at tests/shared_infra_test.cpp:4622 assumes the opposite behavior.

Suggested fix: Remove soffset_val from record_offset and total_offset; retain it only in final address generation. Replace the current SOFFSET test with one proving that changing SOFFSET changes the address without changing the OOB result.

Confidence: high.

I confirmed that this is the public compiler contract documented by LLVM, but this does not match CDNA5's ISA. The ISA explicitly defines offset = sgpr_offset + inst_offset + vgpr_offset, and uses that in total_offset for bounds checking. See 9.4.1 “Range Checking,” Table 56, and the definitions immediately following it. I think we should follow the ISA here, but this may warrent a quick test on hardware, if possible. https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/instruction-set-architectures/amd-instinct-cdna5-instruction-set-architecture.pdf

## Motivation Implement OOB memory access behavior for gfx1250/cdna5. Lay groundwork for other architectures. ## Technical Details - Implemented missing gfx1250’s per-component VBUFFER OOB behavior. - Model CDNA5 descriptor bounds, scaled stride, OOB_SELECT, and 45-bit offset rules. - Implement ordinary aligned, unswizzled TYPE=0 semantics: each dword is checked independently, OOB load components return zero, OOB store components are dropped, atomics remain all-or-nothing, and valid lanes retain coalesced cache traffic. Swizzle, alignment modes/MEMVIOL, and resource-TYPE validation remain follow-ups. ## Issue Tracking N/A ## Test Plan Added new tests. Ran tests. ## Test Result Tests pass. ## Submission Checklist - [x] Look over the contributing guidelines at https://github.com/ROCm/rocm-systems/blob/develop/CONTRIBUTING.md. (cherry picked from commit f81f9d4)

…t calls (#10444) ## Motivation hipTensor and rocThrust gfx1250 objects are refused at code-object load time with "indirect branch or call target recovery is not implemented for relocated kernel text" on `s_swap_pc_i64`. A refused object leaves HIP holding an invalid kernel handle, so the failure surfaces as a segfault rather than a diagnostic. The fix is upstream as #10376; this backports it to `release/bkc/therock-10.1-20260811`. ## Commits Cherry-Picked | # | Upstream | PR | Backport | Subject | |---|----------|-----|----------|---------| | 1 | `b6d838028e` | #10197 | `846fb16d12` | [rocjitsu][docs] Refresh architecture support documentation | | 2 | `5c8e33e391` | #10200 | `db5c58b1be` | [rocjitsu] Define standalone decoder ownership | | 3 | `be1f91998f` | #10199 | `ed102baf1c` | [rocjitsu] Apply async IOFFSET to LDS addresses | | 4 | `fda635e5b4` | — | `ad32ff7c18` | [rocjitsu] Extract per-scope rollback and object-level checks from translate() | | 5 | `8f75eb781e` | — | `4c0cb05207` | [rocjitsu] Emit leading V_NOPs ahead of a gfx1250 MODE write | | 6 | `00aa1e260f` | #9941 | `ded43b1787` | fix(rocjitsu): disable zero-count TDM descriptors | | 7 | `c810647609` | #10192 | `50ca7f1732` | [rocjitsu] Apply MUBUF LDS-load instruction offset to the LDS address | | 8 | `1d7866269d` | #9560 | `2e6bf26943` | [rocjitsu] code rewrite condition validator | | 9 | `95b6c410bb` | #10175 | `8418901076` | [rocjitsu] Fix ds_read_b64_tr_b16 lane layout in gfx950 simulator | | 10 | `bfaebcfb5c` | #10240 | `c4eac1e1f7` | [rocjitsu][util] Add result and diagnostic utilities | | 11 | `dbb7221fa7` | #9775 | `cdd0993a5f` | fix(rocjitsu): route tensor DMA through wave VMID | | 12 | `2779247222` | #9779 | `7bfeba6f5d` | feat(rocjitsu): Lazy vgpr allocation system | | 13 | `a659172a31` | #9936 | `180cf00325` | fix(rocjitsu): honor TDM tensor bounds across iterations | | 14 | `60c29efb39` | #10204 | `370bfb9796` | [rocjitsu] Fix gfx950 decoder extension handling | | 15 | `c1dba564e7` | #10345 | `536110a083` | [rocjitsu] Model gfx1250 wave ABI state | | 16 | `7f71be9f32` | #10346 | `3f922ad5f2` | [rocjitsu] Model gfx1250 barrier synchronization | | 17 | `bea7ac8937` | #10368 | `7b5ecf6c7b` | [rocjitsu] Replace decoder exceptions with results | | 18 | `f2e878694e` | #10371 | `8cf750d23f` | [rocjitsu] Dispatch operand validation by type | | 19 | `dd619bed77` | #9735 | `1a612c47c0` | fix(rocjitsu): respect same-wave LDS ordering | | 20 | `c5fae8d2b2` | #10137 | `4360c4b978` | [rocjitsu] Rename gfx1250 to cdna5 for enums, configs, amdisa codegen helpers and generated symbols. (NFC) | | 21 | `b05a587f89` | #10274 | `bfb5f9fab0` | [rocjitsu] Align CDNA4 MI350X configs with captured topology | | 22 | `f81f9d40db` | #10362 | `8177b5725c` | feat(rocjitsu): cdna5 OOB behavior implementation | | 23 | `53a939bd00` | #10283 | `141b109432` | [rocjitsu] add per-XCD workgroup dispatch observability | | 24 | `a0fb11bc17` | #10414 | `6bb4c5a959` | [rocjitsu] Refactor test encoding handling in execution tests (NFC) | | 25 | `e5109e315e` | #9844 | `322ac26b44` | feat(emulation): debug emulated GPU kernels with real ROCgdb | | 26 | `efa24f23c9` | — | `c3c9641073` | rocjitsu: Point the XCD distribution test at the config that exists | | 27 | `8b7763ef5e` | #10376 | `c3f419555a` | [rocjitsu] Translate gfx1250 lane-banked and kernarg-supplied indirect calls | ## Issue Tracking [ROCM-29436] ## Submission Checklist - [x] Look over the contributing guidelines at https://github.com/ROCm/rocm-systems/blob/develop/CONTRIBUTING.md. [ROCM-29346]: https://amd-hub.atlassian.net/browse/ROCM-29346?atlOrigin=eyJpIjoiNWRkNTljNzYxNjVmNDY3MDlhMDU5Y2ZhYzA5YTRkZjUiLCJwIjoiZ2l0aHViLWNvbS1KU1cifQ [ROCM-29436]: https://amd-hub.atlassian.net/browse/ROCM-29436?atlOrigin=eyJpIjoiNWRkNTljNzYxNjVmNDY3MDlhMDU5Y2ZhYzA5YTRkZjUiLCJwIjoiZ2l0aHViLWNvbS1KU1cifQ --------- Signed-off-by: Tony Gutierrez <anthony.gutierrez@amd.com> Signed-off-by: hanhanW <hanhan0912@gmail.com> Co-authored-by: Jakub Kuderski <jakub@nod-labs.com> Co-authored-by: James Newling <james.newling@gmail.com> Co-authored-by: Fei Kou <feikou@meta.com> Co-authored-by: Austin Lu <austin.lu@amd.com> Co-authored-by: Fei Kou <feikou@anthropic.com> Co-authored-by: Erick Ochoa Lopez <eochoalo@amd.com> Co-authored-by: Han-Chung Wang <hanhan0912@gmail.com> Co-authored-by: Rosa, Ada <arosa@amd.com> Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>

## Motivation Implement OOB memory access behavior for gfx1250/cdna5. Lay groundwork for other architectures. ## Technical Details - Implemented missing gfx1250’s per-component VBUFFER OOB behavior. - Model CDNA5 descriptor bounds, scaled stride, OOB_SELECT, and 45-bit offset rules. - Implement ordinary aligned, unswizzled TYPE=0 semantics: each dword is checked independently, OOB load components return zero, OOB store components are dropped, atomics remain all-or-nothing, and valid lanes retain coalesced cache traffic. Swizzle, alignment modes/MEMVIOL, and resource-TYPE validation remain follow-ups. ## Issue Tracking N/A ## Test Plan Added new tests. Ran tests. ## Test Result Tests pass. ## Submission Checklist - [x] Look over the contributing guidelines at https://github.com/ROCm/rocm-systems/blob/develop/CONTRIBUTING.md.

…10928) ## Motivation CDNA buffer addressing and range checking didn't match gfx950 hardware. This fixes, for CDNA1-4: - SOFFSET and the instruction offset count toward the bounds check (only VOFFSET + inst_offset wraps at 32 bits). - An access must end within NUM_RECORDS, checked per dword for `dwordx{2,3,4}` loads and stores; format ops, atomics and MTBUF stay all-or-nothing. - Only IDXEN uses the index check on a strided buffer; OFFEN-only is checked by byte offset. - ADD_TID_ENABLE buffers add `thread_id * stride` to the address (the DFMT-extended stride for non-format ops) and, with SWIZZLE_ENABLE, use the swizzled element layout; neither is range-checked. - The RDNA OOB_SELECT bit is no longer consulted on CDNA descriptors. - Out-of-range lanes of `buffer_load ... lds` write zeros to LDS instead of being skipped. Previously the simulator ignored SOFFSET, dropped whole lanes, index-checked any strided buffer, gave every lane the same address on ADD_TID_ENABLE buffers, and left LDS untouched. ## Technical Details - `shared/addr_calc_buffer.h`: CDNA1-4 compute the per-lane offset in one helper shared by the MUBUF and MTBUF paths and apply the GFX9 range-check rules; per-dword results go through `element_lane_masks` (#10362) and swizzled multi-dword accesses reuse the scratch per-element stride. RDNA and gfx1250 are unchanged. - `vm/amdgpu/memory_pipeline.cpp`: on CDNA1-4, out-of-range lanes of LDS loads write zeros. The ISA docs and LLVM describe SOFFSET as excluded from the check; gfx950 hardware includes it, so this follows the hardware. DATA_FORMAT = 0 (non-format loads return zeros on hardware) isn't modelled. ## Issue Tracking No existing issue. Related: #10362, #10192. ## Test Plan An encoded-kernel test on cdna1-4 for the range-check cases and one for ADD_TID/swizzled loads and stores (`tests/amdgpu_vm_test.cpp`), direct address-calculation tests on cdna3/cdna4 for each rule (`CdnaAddrCalcTest.Mubuf*`), and one RDNA3 case to confirm that path is unchanged. ## Test Result The new tests fail on `develop` and pass with this change. Expected values were measured on gfx950 (ROCm 7.2). The rest of `ctest` is unchanged and no generated files change. ## Submission Checklist - [x] Look over the contributing guidelines at https://github.com/ROCm/rocm-systems/blob/develop/CONTRIBUTING.md.

The CDNA5 descriptor tests in triton-lang/triton#12512 pass on hardware but fail under Rocjitsu. Crossing raw B128 accesses load and store one extra DWORD near NUM_RECORDS. - CDNA5 buffer bounds (PR #10362, f81f9d4): retain complete accesses, including exact fits, and apply the PR's stated end + 4 <= NUM_RECORDS rule to crossing raw vector accesses. Keep SOFFSET in the check and preserve structured and independent stride bounds. - GFX12 atomic returns (PR #7336, 3a4e98a): test TH[0] independently of the non-temporal and cascade bits. Returning modes 3, 5 and 7 otherwise omit the old value and select non-returning metadata and wait counters. - Signed scratch operands (CDNA5 PR #6673, f6aec50; RDNA4 PR #5053, ca4b97e): sign-extend scalar and vector offsets before combining them and before CDNA5 payload scaling. Compensated negative operands otherwise become large positive private offsets and fault. - CDNA GLOBAL operands (PR #5512, 5a107ce): zero-extend the 32-bit VGPR offset when a scalar base is present. High-bit offsets otherwise resolve four GiB below the intended address. Preserve absolute VGPR pairs and CDNA5 signed addressing. CDNA1-4 manuals and LLVM agree on the unsigned rule. For buffer bounds, the Triton PR measures aligned B128 crossings with four or eight bytes remaining. Other widths and byte-granular bounds follow its stated rule as a model choice pending gfx1250 qualification. Record that limit beside the implementation and regression expectations. Cover bounds, inactive lanes, signed and unsigned operand combinations, atomic writeback and wait counters, including image metadata. Validate 49 Gluon cases with matching ISA and 172 hardware comparisons each on gfx1201 and gfx1100. Audit gfx942/gfx950 buffer, scratch and atomic contracts against the manuals. The standard CTest sweep retains the same 31 baseline failures.

The CDNA5 descriptor tests in triton-lang/triton#12512 pass on hardware but fail under Rocjitsu. Crossing raw B128 accesses load and store one extra DWORD near NUM_RECORDS. - CDNA5 buffer bounds (PR #10362, f81f9d4): retain complete accesses, including exact fits, and apply the PR's stated end + 4 <= NUM_RECORDS rule to crossing raw vector accesses. Keep SOFFSET in the check and preserve structured and independent stride bounds. - GFX12 atomic returns (PR #7336, 3a4e98a): test TH[0] independently of the non-temporal and cascade bits. Returning modes 3, 5 and 7 otherwise omit the old value and select non-returning metadata and wait counters. - Signed scratch operands (CDNA5 PR #6673, f6aec50; RDNA4 PR #5053, ca4b97e): sign-extend scalar and vector offsets before combining them and before CDNA5 payload scaling. Compensated negative operands otherwise become large positive private offsets and fault. - CDNA GLOBAL operands (PR #5512, 5a107ce): zero-extend the 32-bit VGPR offset when a scalar base is present. High-bit offsets otherwise resolve four GiB below the intended address. Preserve absolute VGPR pairs and CDNA5 signed addressing. CDNA1-4 manuals and LLVM agree on the unsigned rule. - PC exports and targets (import handling #9844, e5109e3): apply the architecture's extension rule to GETPC, CALL and SWAPPC return addresses. RDNA4 zero-extends 48 bits; older targets sign-extend 48 bits and CDNA5 sign-extends 57 bits. Keep imported PCs as raw 48/57-bit addresses for instruction fetch, consistent with RFE, and preserve all CDNA5 target bits. Limit the positive linked-rel32 tag to 48-bit targets. Remove the negative tag on every target: it aliases ordinary sign-filled PC exports. Both forms otherwise corrupt valid 57-bit targets or older high-PC round trips when a load bias is present. For buffer bounds, the Triton PR measures aligned B128 crossings with four or eight bytes remaining. Other widths and byte-granular bounds follow its stated rule as a model choice pending gfx1250 qualification. Record that limit beside the implementation and regression expectations. Cover bounds, inactive lanes, signed and unsigned operand combinations, atomic writeback and wait counters, including image metadata. Validate 49 Gluon cases with matching ISA and 172 hardware comparisons each on gfx1201 and gfx1100. Audit gfx942/gfx950 buffer, scratch and atomic contracts against the manuals. The standard CTest sweep retains the same 31 baseline failures. Decode and execute PC regression cases on gfx1100, gfx1201, gfx950 and gfx1250, including high address bits, next-PC boundaries and operand aliasing. Follow SETPC/SWAPPC through real page tables to fetch a high mapped destination, including both relocation-tag collisions with a nonzero load bias. Older linked-rel32 debugger coverage is retained. These are manual/LLVM-backed simulation checks without physical high-address PC qualification. RDNA3/3.5 sign-filled exports follow LLVM against conflicting manual tables; record that choice beside the generator and test oracle. Add explicit test braces for GCC.

…14352) The CDNA5 descriptor tests in [triton-lang/triton#12512](triton-lang/triton#12512) pass on hardware but fail under Rocjitsu. Crossing raw B128 accesses load and store one extra DWORD near `NUM_RECORDS`. Auditing neighboring instructions and extension rules across gfx942/gfx950, gfx1100/gfx1201 and gfx1250 exposed further address and return defects. - **CDNA5 buffer bounds** (introduced by #10362, `f81f9d40db67`): keep complete accesses, including exact fits, and apply the Triton PR's stated `end + 4 <= NUM_RECORDS` rule to crossing raw vector accesses. Count `SOFFSET` and preserve structured and independent stride checks. - **GFX12 atomic returns** (introduced by #7336, `3a4e98a167e6`): test `TH[0]` independently of the non-temporal and cascade bits. Return modes 3, 5 and 7 otherwise omit the old value and select non-returning metadata and wait counters. - **GFX12 scratch operands** (CDNA5 #6673, `f6aec5064565`; RDNA4 #5053, `ca4b97ef2cc6`): sign-extend scalar/vector inputs before combining them and before CDNA5 payload scaling. Compensated negative inputs otherwise become large positive private offsets and fault. - **CDNA1–4 GLOBAL operands** (introduced by #5512, `5a107cebd601`): zero-extend the 32-bit VGPR offset when a scalar base is present. High-bit offsets otherwise address four GiB below the intended location. Preserve absolute VGPR pairs and the separate CDNA5 signed rule. - **PC extension and width**: GETPC, CALL and SWAPPC now export signed 48-bit PCs on older targets, zero-filled 48-bit PCs on RDNA4, and signed 57-bit PCs on CDNA5. SETPC/SWAPPC use raw masked 48/57-bit internal addresses so high targets remain fetchable through page tables. CDNA5 keeps all 57 target bits and bypasses linked-rel32 tags. The ambiguous negative tag is removed on every target so sign-filled PC exports round-trip with a load bias; 48-bit targets retain the positive tag covered by gfx950 debugger integration. Previously high PCs exposed the wrong upper bits or lost valid target bits. The generator and its 40 emitted PC handlers agree. RDNA3/3.5 sign-filled exports follow LLVM against conflicting manual tables; high-address PC behavior has no physical qualification. The gfx1250 buffer evidence covers aligned B128 crossings with four/eight bytes remaining. Other widths and byte-granular bounds follow the Triton PR's stated rule as model choices pending gfx1250 hardware qualification; the source and tests say so explicitly. The gfx942/gfx950 manual audit preserves the existing legacy scratch policy where no legal allocated-input mismatch was demonstrated. Local validation: - 49 Gluon cases pass through matching descriptor/instruction ISA. The installed Triton predates the new descriptor frontend API, so this is an ISA-equivalent replay, not a rebuild of that API. - 172 saved physical gfx1201 comparisons and 172 physical gfx1100 comparisons match simulation: buffer bounds, atomic return controls, legal scratch operands and GLOBAL offsets. The buffer-clamp rule remains CDNA5-specific. - gfx942 and gfx950 buffer/atomic/scratch/GLOBAL contracts were checked against their manuals and LLVM. All eight compiled HIP GLOBAL load/store simulation cases pass; no physical gfx942/gfx950 qualification is claimed. - 28 PC test groups cover gfx1100/gfx1201/gfx950/gfx1250, including next-PC boundaries, target width and SWAPPC operand aliasing. The original handlers fail 11 of the initial 16 groups. Page-table-backed fetch and nonzero-load-bias tests also reproduce the additional import/relocation gaps; all 28 final PC groups pass, including GETPC-to-SETPC/SWAPPC round trips with a nonzero load bias. Encodings were independently verified with LLVM. Four groups execute the destination through real page tables, including both 57-bit relocation-tag collisions. These are source-backed simulation checks without physical high-address PC qualification. - After rebasing onto current `develop`, the project builds and all 2,851 generator checks pass, with 46 skipped. Earlier GCC syntax checks cover the atomic and PC test translation units with `-Werror=dangling-else`; explicit braces fix the reported CI build error. Changed-file formatting hooks pass. - Rebase validation passes all 313 focused CTests, including PC, address, atomic and newly landed fork/join coverage. Standard CTest retains exactly the same 31 baseline failure names and classifications: 31/9181 after rebasing versus 31/9010 before rebasing. No new failure names.

lua1235 requested review from a team and atgutier as code owners August 18, 2026 21:45

github-actions Bot added the project: rocjitsu label Aug 18, 2026

therock-pr-bot Bot added the Not ready to Review label Aug 18, 2026

systems-assistant Bot added the organization: ROCm label Aug 18, 2026

atgutier reviewed Aug 18, 2026

View reviewed changes

kuhar reviewed Aug 19, 2026

View reviewed changes

Comment thread emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.cpp Resolved

lua1235 added 2 commits August 19, 2026 17:39

OOB behavior implementation

a202a55

Negative IOFFSET early return

536c4b2

lua1235 force-pushed the users/lua1235/gfx1250-partial-oob branch from 1f3464e to 536c4b2 Compare August 19, 2026 17:43

kuhar approved these changes Aug 19, 2026

View reviewed changes

kuhar merged commit f81f9d4 into develop Aug 19, 2026
32 of 33 checks passed

kuhar deleted the users/lua1235/gfx1250-partial-oob branch August 19, 2026 19:01

newling mentioned this pull request Aug 19, 2026

[rocjitsu] Model gfx1250 SRAM ECC semantics for D16 loads #10445

Merged

atgutier mentioned this pull request Aug 19, 2026

[rocjitsu] Translate gfx1250 lane-banked and kernarg-supplied indirect calls #10444

Merged

1 task done

feikou mentioned this pull request Aug 29, 2026

[rocjitsu] Model GFX9/CDNA buffer range check and ADD_TID addressing #10928

Merged

1 task done

kuhar mentioned this pull request Oct 27, 2026

[rocjitsu] Fix AMDGPU buffer bounds, atomic returns and addressing #14352

Merged

Navigation Menu

Repository navigation

feat(rocjitsu): cdna5 OOB behavior implementation - #10362

feat(rocjitsu): cdna5 OOB behavior implementation#10362
kuhar merged 2 commits into
developfrom
users/lua1235/gfx1250-partial-oob

lua1235 commented Aug 18, 2026

Uh oh!

therock-pr-bot Bot commented Aug 18, 2026 •

edited

Loading

Uh oh!

therock-pr-bot Bot commented Aug 18, 2026

Uh oh!

atgutier left a comment

Uh oh!

kuhar left a comment

Uh oh!

Uh oh!

lua1235 commented Aug 19, 2026

Uh oh!

Uh oh!

Reviewers

Uh oh!

Assignees

Labels

Projects

Milestone

Development

Uh oh!

3 participants

Conversation

lua1235 commented Aug 18, 2026

Motivation

Technical Details

Issue Tracking

Test Plan

Test Result

Submission Checklist

Uh oh!

therock-pr-bot Bot commented Aug 18, 2026 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

❌ PR Check — Action Required

Uh oh!

therock-pr-bot Bot commented Aug 18, 2026

Uh oh!

atgutier left a comment

Choose a reason for hiding this comment

Uh oh!

kuhar left a comment

Choose a reason for hiding this comment

Uh oh!

Uh oh!

lua1235 commented Aug 19, 2026

Uh oh!

Uh oh!

Reviewers

Uh oh!

Assignees

Labels

Projects

Milestone

Development

Uh oh!

3 participants

therock-pr-bot Bot commented Aug 18, 2026 •

edited

Loading