[rocjitsu] Model gfx1250 wave ABI state by kuhar · Pull Request #10345 · ROCm/rocm-systems

kuhar · 2026-08-18T20:02:31Z

Model the architectural wave state that gfx1250 compiler-generated kernels and debugger paths consume instead of relying on legacy scalar register conventions.

Treat scalar selectors 102 and 103 as ordinary SGPRs on GFX10+ targets, preserve Wave32 VCC_HI scratch across vector predicate and carry writes, and expose explicit masked VCC access for VCCZ. Keep the flat-scratch encoding policy architecture-explicit so unknown future targets do not inherit the legacy alias.

Populate the gfx1250 TTMP launch payload from the AQL dispatch: encode the queue packet index, wave-in-workgroup position, and Y/Z validity in TTMP8, while retaining the architected workgroup and cluster coordinates in TTMP6, TTMP7, and TTMP9. Extend execution and dispatch tests across every scalar resolver direction, both VCC execution paths, one- and two-dimensional TTMP layouts, and nonzero queue slots.

Model the architectural wave state that gfx1250 compiler-generated kernels and debugger paths consume instead of relying on legacy scalar register conventions. Treat scalar selectors 102 and 103 as ordinary SGPRs on GFX10+ targets, preserve Wave32 VCC_HI scratch across vector predicate and carry writes, and expose explicit masked VCC access for VCCZ. Keep the flat-scratch encoding policy architecture-explicit so unknown future targets do not inherit the legacy alias. Populate the gfx1250 TTMP launch payload from the AQL dispatch: encode the queue packet index, wave-in-workgroup position, and Y/Z validity in TTMP8, while retaining the architected workgroup and cluster coordinates in TTMP6, TTMP7, and TTMP9. Extend execution and dispatch tests across every scalar resolver direction, both VCC execution paths, one- and two-dimensional TTMP layouts, and nonzero queue slots.

therock-pr-bot · 2026-08-18T20:03:11Z

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Copilot

Pull request overview

This PR updates rocjitsu’s gfx1250 (GFX12.5) emulation to model the architectural “wave state” (SGPR selectors, VCC/EXEC semantics, and TTMP launch payload) that compiler-generated kernels and debugger flows consume, rather than relying on legacy aliasing rules.

Changes:

Make scalar selectors 102/103 behave as normal SGPRs on GFX10+ (including gfx1250) by gating the legacy FLAT_SCRATCH alias behind an explicit per-arch trait.
Preserve Wave32 non-lane bits (scratch) when vector instructions write VCC by introducing vcc_mask / set_vcc_mask and migrating vector predicate/carry producers to use it.
Populate gfx1250 TTMP8 from AQL dispatch metadata (queue packet slot id, wave-in-workgroup, and a Y/Z-valid flag) and extend simulation/execution tests to cover the new behavior.

Reviewed changes

Copilot reviewed 13 out of 22 changed files in this pull request and generated no comments.

Show a summary per file

File	Description
emulation/rocjitsu/tests/cdna5_execution_test.cpp	Adds execution-level tests for SGPR 102/103 behavior and Wave32 VCC_HI preservation.
emulation/rocjitsu/tests/cdna5_dispatch_memory_test.cpp	Adds dispatch/snapshot tests validating TTMP8 encoding (wave id and queue packet id) and Y/Z-valid flag.
emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.h	Adds `vcc_mask()` / `set_vcc_mask()` to preserve Wave32 non-lane bits; clarifies raw vs masked semantics.
emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/dispatch_entry.h	Extends dispatch metadata with `queue_packet_id` and `grid_yz_valid`.
emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.h	Updates `process_aql_packet` signature to accept a queue packet slot id.
emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.cpp	Writes TTMP8 fields and plumbs queue packet id / YZ-valid metadata through DispatchEntry.
emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/isa_traits.h	Introduces `arch_uses_legacy_flat_scratch_sgprs()` to make the 102/103 alias architecture-explicit.
emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/simd_glue.h	Switches vector carry/predicate writers from `set_vcc` to `set_vcc_mask`.
emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/scalar_operand_resolve.h	Gates legacy 102/103 scratch aliasing by architecture; uses `vcc_mask()` for VCCZ.
emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/shared/execute_shared.h	Updates generated vector execution helpers to use `set_vcc_mask` when producing VCC.
emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vopc_exec.cpp	Migrates cmpx VCC writes to `set_vcc_mask`.
emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop3_exec.cpp	Migrates cmpx VCC writes to `set_vcc_mask`.
emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vopc_exec.cpp	Migrates cmpx VCC writes to `set_vcc_mask`.
emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop3_exec.cpp	Migrates cmpx VCC writes to `set_vcc_mask`.
emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vopc_exec.cpp	Migrates cmpx VCC writes to `set_vcc_mask`.
emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop3_exec.cpp	Migrates cmpx VCC writes to `set_vcc_mask`.
emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vopc_exec.cpp	Migrates cmpx VCC writes to `set_vcc_mask`.
emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop3_exec.cpp	Migrates cmpx VCC writes to `set_vcc_mask`.
emulation/rocjitsu/lib/python/amdisa/tests/test_gen_vector_cmpx.py	Updates codegen contract checks to expect `set_vcc_mask` emissions.
emulation/rocjitsu/lib/python/amdisa/codegen/execute/vector_special.py	Emits `set_vcc_mask` for div/scale VCC writes.
emulation/rocjitsu/lib/python/amdisa/codegen/execute/vector_cmp.py	Emits `set_vcc_mask` for vector compare/cmpx and carry-producing paths when writing VCC.
emulation/rocjitsu/lib/python/amdisa/codegen/execute/sema_lower.py	Updates lowering to generate `set_vcc_mask` in VCC-write statements.

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newling

LGTM. An agent review (here) suggests that there is another PR from #10335 with a similar but different fix. The agent review also suggested more tests, and mentions an assertion that #10335 adds that this PR does not. All seem minor to me.

atgutier

LGTM

amd-arosa · 2026-08-18T21:52:46Z

closing #10335 in favor of this pr.

amd-arosa

i recommend copying tests from #10335

Model the architectural wave state that gfx1250 compiler-generated kernels and debugger paths consume instead of relying on legacy scalar register conventions. Treat scalar selectors 102 and 103 as ordinary SGPRs on GFX10+ targets, preserve Wave32 VCC_HI scratch across vector predicate and carry writes, and expose explicit masked VCC access for VCCZ. Keep the flat-scratch encoding policy architecture-explicit so unknown future targets do not inherit the legacy alias. Populate the gfx1250 TTMP launch payload from the AQL dispatch: encode the queue packet index, wave-in-workgroup position, and Y/Z validity in TTMP8, while retaining the architected workgroup and cluster coordinates in TTMP6, TTMP7, and TTMP9. Extend execution and dispatch tests across every scalar resolver direction, both VCC execution paths, one- and two-dimensional TTMP layouts, and nonzero queue slots. (cherry picked from commit c1dba56)

…t calls (#10444) ## Motivation hipTensor and rocThrust gfx1250 objects are refused at code-object load time with "indirect branch or call target recovery is not implemented for relocated kernel text" on `s_swap_pc_i64`. A refused object leaves HIP holding an invalid kernel handle, so the failure surfaces as a segfault rather than a diagnostic. The fix is upstream as #10376; this backports it to `release/bkc/therock-10.1-20260811`. ## Commits Cherry-Picked | # | Upstream | PR | Backport | Subject | |---|----------|-----|----------|---------| | 1 | `b6d838028e` | #10197 | `846fb16d12` | [rocjitsu][docs] Refresh architecture support documentation | | 2 | `5c8e33e391` | #10200 | `db5c58b1be` | [rocjitsu] Define standalone decoder ownership | | 3 | `be1f91998f` | #10199 | `ed102baf1c` | [rocjitsu] Apply async IOFFSET to LDS addresses | | 4 | `fda635e5b4` | — | `ad32ff7c18` | [rocjitsu] Extract per-scope rollback and object-level checks from translate() | | 5 | `8f75eb781e` | — | `4c0cb05207` | [rocjitsu] Emit leading V_NOPs ahead of a gfx1250 MODE write | | 6 | `00aa1e260f` | #9941 | `ded43b1787` | fix(rocjitsu): disable zero-count TDM descriptors | | 7 | `c810647609` | #10192 | `50ca7f1732` | [rocjitsu] Apply MUBUF LDS-load instruction offset to the LDS address | | 8 | `1d7866269d` | #9560 | `2e6bf26943` | [rocjitsu] code rewrite condition validator | | 9 | `95b6c410bb` | #10175 | `8418901076` | [rocjitsu] Fix ds_read_b64_tr_b16 lane layout in gfx950 simulator | | 10 | `bfaebcfb5c` | #10240 | `c4eac1e1f7` | [rocjitsu][util] Add result and diagnostic utilities | | 11 | `dbb7221fa7` | #9775 | `cdd0993a5f` | fix(rocjitsu): route tensor DMA through wave VMID | | 12 | `2779247222` | #9779 | `7bfeba6f5d` | feat(rocjitsu): Lazy vgpr allocation system | | 13 | `a659172a31` | #9936 | `180cf00325` | fix(rocjitsu): honor TDM tensor bounds across iterations | | 14 | `60c29efb39` | #10204 | `370bfb9796` | [rocjitsu] Fix gfx950 decoder extension handling | | 15 | `c1dba564e7` | #10345 | `536110a083` | [rocjitsu] Model gfx1250 wave ABI state | | 16 | `7f71be9f32` | #10346 | `3f922ad5f2` | [rocjitsu] Model gfx1250 barrier synchronization | | 17 | `bea7ac8937` | #10368 | `7b5ecf6c7b` | [rocjitsu] Replace decoder exceptions with results | | 18 | `f2e878694e` | #10371 | `8cf750d23f` | [rocjitsu] Dispatch operand validation by type | | 19 | `dd619bed77` | #9735 | `1a612c47c0` | fix(rocjitsu): respect same-wave LDS ordering | | 20 | `c5fae8d2b2` | #10137 | `4360c4b978` | [rocjitsu] Rename gfx1250 to cdna5 for enums, configs, amdisa codegen helpers and generated symbols. (NFC) | | 21 | `b05a587f89` | #10274 | `bfb5f9fab0` | [rocjitsu] Align CDNA4 MI350X configs with captured topology | | 22 | `f81f9d40db` | #10362 | `8177b5725c` | feat(rocjitsu): cdna5 OOB behavior implementation | | 23 | `53a939bd00` | #10283 | `141b109432` | [rocjitsu] add per-XCD workgroup dispatch observability | | 24 | `a0fb11bc17` | #10414 | `6bb4c5a959` | [rocjitsu] Refactor test encoding handling in execution tests (NFC) | | 25 | `e5109e315e` | #9844 | `322ac26b44` | feat(emulation): debug emulated GPU kernels with real ROCgdb | | 26 | `efa24f23c9` | — | `c3c9641073` | rocjitsu: Point the XCD distribution test at the config that exists | | 27 | `8b7763ef5e` | #10376 | `c3f419555a` | [rocjitsu] Translate gfx1250 lane-banked and kernarg-supplied indirect calls | ## Issue Tracking [ROCM-29436] ## Submission Checklist - [x] Look over the contributing guidelines at https://github.com/ROCm/rocm-systems/blob/develop/CONTRIBUTING.md. [ROCM-29346]: https://amd-hub.atlassian.net/browse/ROCM-29346?atlOrigin=eyJpIjoiNWRkNTljNzYxNjVmNDY3MDlhMDU5Y2ZhYzA5YTRkZjUiLCJwIjoiZ2l0aHViLWNvbS1KU1cifQ [ROCM-29436]: https://amd-hub.atlassian.net/browse/ROCM-29436?atlOrigin=eyJpIjoiNWRkNTljNzYxNjVmNDY3MDlhMDU5Y2ZhYzA5YTRkZjUiLCJwIjoiZ2l0aHViLWNvbS1KU1cifQ --------- Signed-off-by: Tony Gutierrez <anthony.gutierrez@amd.com> Signed-off-by: hanhanW <hanhan0912@gmail.com> Co-authored-by: Jakub Kuderski <jakub@nod-labs.com> Co-authored-by: James Newling <james.newling@gmail.com> Co-authored-by: Fei Kou <feikou@meta.com> Co-authored-by: Austin Lu <austin.lu@amd.com> Co-authored-by: Fei Kou <feikou@anthropic.com> Co-authored-by: Erick Ochoa Lopez <eochoalo@amd.com> Co-authored-by: Han-Chung Wang <hanhan0912@gmail.com> Co-authored-by: Rosa, Ada <arosa@amd.com> Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>

Model the architectural wave state that gfx1250 compiler-generated kernels and debugger paths consume instead of relying on legacy scalar register conventions. Treat scalar selectors 102 and 103 as ordinary SGPRs on GFX10+ targets, preserve Wave32 VCC_HI scratch across vector predicate and carry writes, and expose explicit masked VCC access for VCCZ. Keep the flat-scratch encoding policy architecture-explicit so unknown future targets do not inherit the legacy alias. Populate the gfx1250 TTMP launch payload from the AQL dispatch: encode the queue packet index, wave-in-workgroup position, and Y/Z validity in TTMP8, while retaining the architected workgroup and cluster coordinates in TTMP6, TTMP7, and TTMP9. Extend execution and dispatch tests across every scalar resolver direction, both VCC execution paths, one- and two-dimensional TTMP layouts, and nonzero queue slots.

kuhar requested review from lua1235 and newling August 18, 2026 20:02

kuhar requested review from a team and atgutier as code owners August 18, 2026 20:02

Copilot AI lite review requested due to automatic review settings August 18, 2026 20:02

github-actions Bot added the project: rocjitsu label Aug 18, 2026

Copilot started reviewing on behalf of kuhar August 18, 2026 20:03

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newling approved these changes Aug 18, 2026

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kuhar merged commit c1dba56 into develop Aug 18, 2026
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kuhar deleted the users/kuhar/gfx1250-wave-state-fixes branch August 18, 2026 23:19

atgutier mentioned this pull request Aug 19, 2026

[rocjitsu] Translate gfx1250 lane-banked and kernarg-supplied indirect calls #10444

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This was referenced Aug 26, 2026

fix(rocjitsu): finish TTMP selector routing #10786

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refactor(rocjitsu): make instruction register access wave-owned #10030

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[rocjitsu] Model gfx1250 wave ABI state - #10345

[rocjitsu] Model gfx1250 wave ABI state#10345
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