fix(rocjitsu): disable zero-count TDM descriptors by newling · Pull Request #9941 · ROCm/rocm-systems

newling · 2026-08-10T21:34:15Z

Summary

This small change makes tensor-DMA load and store operations honor a zero
descriptor count as a disabled transfer.

The gap was found while reducing the stock gfx1250 TensileLite TDM workload
tracked by #9935. Generated TensileLite code explicitly writes zero to the
descriptor Group 0 count field when disabling TDM loads in the final prefetch
iterations, but rocJITsu previously ignored that field and executed the
transfer.

Related contract evidence

Enable HalfPLR for MXF8 in gfx1250 rocm-libraries#7453 introduced the HalfPLR TDM disable convention by
conditionally clearing descriptor Group 0 and restoring it before the tail
loop.
[rocjitsu] Fix gfx1250 TDM barrier completion #7361 established the shared TDM wait-counter and atomic
barrier sequencing that this PR preserves inside the common load/store
executor.

Failure before this fix

A descriptor that generated code had disabled could still copy global data
into LDS or store LDS data to global memory. If the descriptor requested an
atomic-barrier arrival, that side effect was also performed.

Fix

Parse the two-bit count field from descriptor Group 0.
Represent descriptor activity as part of the parsed descriptor contract.
Route load and store through one common tensor-DMA executor, which performs
no copy or barrier side effect for an inactive descriptor.

Test coverage

The focused regression initializes global memory, LDS, and an atomic barrier
with distinct values, executes decoded load and store instructions, and
verifies that both operations leave all three unchanged. Existing tensor-DMA
execution tests continue to pass.

Workload status

This PR fixes one independent descriptor contract. It does not claim to resolve
the complete TensileLite reproducer or the remaining tail-loop semantic
question.

Issue tracking

Progress toward #9935.

therock-pr-bot · 2026-08-10T21:35:18Z

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therock-pr-bot · 2026-08-10T21:35:52Z

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kuhar

One small suggestion

atgutier

LGTM

kuhar

LGTM

## Summary This small change makes tensor-DMA load and store operations honor a zero descriptor count as a disabled transfer. The gap was found while reducing the stock gfx1250 TensileLite TDM workload tracked by #9935. Generated TensileLite code explicitly writes zero to the descriptor Group 0 count field when disabling TDM loads in the final prefetch iterations, but rocJITsu previously ignored that field and executed the transfer. ## Related contract evidence - ROCm/rocm-libraries#7453 introduced the HalfPLR TDM disable convention by conditionally clearing descriptor Group 0 and restoring it before the tail loop. - #7361 established the shared TDM wait-counter and atomic barrier sequencing that this PR preserves inside the common load/store executor. ## Failure before this fix A descriptor that generated code had disabled could still copy global data into LDS or store LDS data to global memory. If the descriptor requested an atomic-barrier arrival, that side effect was also performed. ## Fix - Parse the two-bit count field from descriptor Group 0. - Represent descriptor activity as part of the parsed descriptor contract. - Route load and store through one common tensor-DMA executor, which performs no copy or barrier side effect for an inactive descriptor. ## Test coverage The focused regression initializes global memory, LDS, and an atomic barrier with distinct values, executes decoded load and store instructions, and verifies that both operations leave all three unchanged. Existing tensor-DMA execution tests continue to pass. ## Workload status This PR fixes one independent descriptor contract. It does not claim to resolve the complete TensileLite reproducer or the remaining tail-loop semantic question. ## Issue tracking Progress toward #9935. (cherry picked from commit 00aa1e2)

…t calls (#10444) ## Motivation hipTensor and rocThrust gfx1250 objects are refused at code-object load time with "indirect branch or call target recovery is not implemented for relocated kernel text" on `s_swap_pc_i64`. A refused object leaves HIP holding an invalid kernel handle, so the failure surfaces as a segfault rather than a diagnostic. The fix is upstream as #10376; this backports it to `release/bkc/therock-10.1-20260811`. ## Commits Cherry-Picked | # | Upstream | PR | Backport | Subject | |---|----------|-----|----------|---------| | 1 | `b6d838028e` | #10197 | `846fb16d12` | [rocjitsu][docs] Refresh architecture support documentation | | 2 | `5c8e33e391` | #10200 | `db5c58b1be` | [rocjitsu] Define standalone decoder ownership | | 3 | `be1f91998f` | #10199 | `ed102baf1c` | [rocjitsu] Apply async IOFFSET to LDS addresses | | 4 | `fda635e5b4` | — | `ad32ff7c18` | [rocjitsu] Extract per-scope rollback and object-level checks from translate() | | 5 | `8f75eb781e` | — | `4c0cb05207` | [rocjitsu] Emit leading V_NOPs ahead of a gfx1250 MODE write | | 6 | `00aa1e260f` | #9941 | `ded43b1787` | fix(rocjitsu): disable zero-count TDM descriptors | | 7 | `c810647609` | #10192 | `50ca7f1732` | [rocjitsu] Apply MUBUF LDS-load instruction offset to the LDS address | | 8 | `1d7866269d` | #9560 | `2e6bf26943` | [rocjitsu] code rewrite condition validator | | 9 | `95b6c410bb` | #10175 | `8418901076` | [rocjitsu] Fix ds_read_b64_tr_b16 lane layout in gfx950 simulator | | 10 | `bfaebcfb5c` | #10240 | `c4eac1e1f7` | [rocjitsu][util] Add result and diagnostic utilities | | 11 | `dbb7221fa7` | #9775 | `cdd0993a5f` | fix(rocjitsu): route tensor DMA through wave VMID | | 12 | `2779247222` | #9779 | `7bfeba6f5d` | feat(rocjitsu): Lazy vgpr allocation system | | 13 | `a659172a31` | #9936 | `180cf00325` | fix(rocjitsu): honor TDM tensor bounds across iterations | | 14 | `60c29efb39` | #10204 | `370bfb9796` | [rocjitsu] Fix gfx950 decoder extension handling | | 15 | `c1dba564e7` | #10345 | `536110a083` | [rocjitsu] Model gfx1250 wave ABI state | | 16 | `7f71be9f32` | #10346 | `3f922ad5f2` | [rocjitsu] Model gfx1250 barrier synchronization | | 17 | `bea7ac8937` | #10368 | `7b5ecf6c7b` | [rocjitsu] Replace decoder exceptions with results | | 18 | `f2e878694e` | #10371 | `8cf750d23f` | [rocjitsu] Dispatch operand validation by type | | 19 | `dd619bed77` | #9735 | `1a612c47c0` | fix(rocjitsu): respect same-wave LDS ordering | | 20 | `c5fae8d2b2` | #10137 | `4360c4b978` | [rocjitsu] Rename gfx1250 to cdna5 for enums, configs, amdisa codegen helpers and generated symbols. (NFC) | | 21 | `b05a587f89` | #10274 | `bfb5f9fab0` | [rocjitsu] Align CDNA4 MI350X configs with captured topology | | 22 | `f81f9d40db` | #10362 | `8177b5725c` | feat(rocjitsu): cdna5 OOB behavior implementation | | 23 | `53a939bd00` | #10283 | `141b109432` | [rocjitsu] add per-XCD workgroup dispatch observability | | 24 | `a0fb11bc17` | #10414 | `6bb4c5a959` | [rocjitsu] Refactor test encoding handling in execution tests (NFC) | | 25 | `e5109e315e` | #9844 | `322ac26b44` | feat(emulation): debug emulated GPU kernels with real ROCgdb | | 26 | `efa24f23c9` | — | `c3c9641073` | rocjitsu: Point the XCD distribution test at the config that exists | | 27 | `8b7763ef5e` | #10376 | `c3f419555a` | [rocjitsu] Translate gfx1250 lane-banked and kernarg-supplied indirect calls | ## Issue Tracking [ROCM-29436] ## Submission Checklist - [x] Look over the contributing guidelines at https://github.com/ROCm/rocm-systems/blob/develop/CONTRIBUTING.md. [ROCM-29346]: https://amd-hub.atlassian.net/browse/ROCM-29346?atlOrigin=eyJpIjoiNWRkNTljNzYxNjVmNDY3MDlhMDU5Y2ZhYzA5YTRkZjUiLCJwIjoiZ2l0aHViLWNvbS1KU1cifQ [ROCM-29436]: https://amd-hub.atlassian.net/browse/ROCM-29436?atlOrigin=eyJpIjoiNWRkNTljNzYxNjVmNDY3MDlhMDU5Y2ZhYzA5YTRkZjUiLCJwIjoiZ2l0aHViLWNvbS1KU1cifQ --------- Signed-off-by: Tony Gutierrez <anthony.gutierrez@amd.com> Signed-off-by: hanhanW <hanhan0912@gmail.com> Co-authored-by: Jakub Kuderski <jakub@nod-labs.com> Co-authored-by: James Newling <james.newling@gmail.com> Co-authored-by: Fei Kou <feikou@meta.com> Co-authored-by: Austin Lu <austin.lu@amd.com> Co-authored-by: Fei Kou <feikou@anthropic.com> Co-authored-by: Erick Ochoa Lopez <eochoalo@amd.com> Co-authored-by: Han-Chung Wang <hanhan0912@gmail.com> Co-authored-by: Rosa, Ada <arosa@amd.com> Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>

github-actions Bot added the project: rocjitsu label Aug 10, 2026

newling mentioned this pull request Aug 10, 2026

[rocjitsu][gfx1250] Stock TensileLite TDM tail test does not complete under full simulation #9935

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systems-assistant Bot added the organization: ROCm label Aug 10, 2026

newling force-pushed the fix/gfx1250-tdm-zero-count-disablement branch 3 times, most recently from fbe625c to 0574d70 Compare August 10, 2026 23:34

newling marked this pull request as ready for review August 11, 2026 00:11

newling requested review from a team and atgutier as code owners August 11, 2026 00:11

newling force-pushed the fix/gfx1250-tdm-zero-count-disablement branch from 0574d70 to 2db2af4 Compare August 11, 2026 19:24

kuhar reviewed Aug 11, 2026

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Comment thread emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/tensor_dma.h Resolved

newling force-pushed the fix/gfx1250-tdm-zero-count-disablement branch from 2db2af4 to 1a6649a Compare August 11, 2026 22:44

newling requested a review from kuhar August 11, 2026 22:46

atgutier approved these changes Aug 12, 2026

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newling force-pushed the fix/gfx1250-tdm-zero-count-disablement branch from 1a6649a to 3f2ff29 Compare August 13, 2026 14:59

kuhar approved these changes Aug 13, 2026

View reviewed changes

newling force-pushed the fix/gfx1250-tdm-zero-count-disablement branch from 3f2ff29 to 17623d4 Compare August 13, 2026 15:36

newling added 2 commits August 14, 2026 16:03

fix(rocjitsu): disable zero-count TDM descriptors

9352152

fix(rocjitsu): reject unsupported TDM count encodings

abdd743

newling force-pushed the fix/gfx1250-tdm-zero-count-disablement branch from 17623d4 to abdd743 Compare August 14, 2026 23:16

newling merged commit 00aa1e2 into ROCm:develop Aug 17, 2026
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atgutier mentioned this pull request Aug 19, 2026

[rocjitsu] Translate gfx1250 lane-banked and kernarg-supplied indirect calls #10444

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fix(rocjitsu): disable zero-count TDM descriptors - #9941

fix(rocjitsu): disable zero-count TDM descriptors#9941
newling merged 2 commits into
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newling:fix/gfx1250-tdm-zero-count-disablement

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Summary

Related contract evidence

Failure before this fix

Fix

Test coverage

Workload status

Issue tracking

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