[newling]

Summary

This change fixes tensor-DMA bounds contracts exposed while reducing the stock gfx1250 TensileLite TDM tail failure tracked by #9935.

It is independent of the VMID correction in #9775 at the source level. Both changes are needed to advance the original workload through the currently known rocJITsu model gaps.

Related producer-side evidence

• [tensilelite] Support TDM iterate mode rocm-libraries#7976 introduced TDM iterate mode and the tdm_gfx1250.yaml configuration lineage that exposed this gap.
• Fix 2 kernel bugs rocm-libraries#8406 contains the same affected configuration after iterate mode was enabled and reports passing FFM and B0 validation. This is file-level evidence rather than a published per-solution trace.
• feat(tensilelite): subtile kernel enable tdm iterate mode for large depthu rocm-libraries#9410 added iterate-mode edge cases with waves that have zero valid rows specifically to exercise descriptor bounds clamping, and reports passing FFM validation.

Failure before this fix

Iterate mode advanced the starting global address for each repeated tile, but rocJITsu continued to apply bounds using tile-local coordinates. A final row outside the tensor was therefore copied into LDS instead of being zero-filled.

An active tensor extent of zero was treated as unbounded. The complete dense or gather tile could therefore be copied instead of being masked.

Fixes

Include iterate-mode address advancement in tensor bounds

The model decomposes each advancing iteration's linear global-address increment into an absolute tensor-coordinate origin, then applies one bounds predicate to that origin plus the tile-local coordinate.

This handles sub-row advances, row advances, and rank-3 plane advances through the same path. Overlapping-stride layouts are rejected only when multiple iterations actually advance the global origin; repeated-origin descriptors do not require inverse coordinate decomposition.

Treat zero active tensor extents as empty

For an active dense or gather tile dimension, tensor extent zero masks the complete dimension. Loads zero-fill the affected LDS elements and stores suppress the corresponding global writes.

Optional null descriptor groups retain their architectural zero-filled value. A rank-3 tile with null D2 therefore has a zero third tensor extent: it masks the transfer without aborting execution, still completes an enabled barrier, and releases TENSORCNT normally.

Avoid unnecessary origin decomposition

Non-iterating descriptors use an all-zero origin directly. This avoids inverse stride decomposition, including accepted rank-5 layouts whose large default strides can wrap.

Test coverage

Focused decoded-instruction regressions verify:

• partial final-row load zero-fill and corresponding store suppression;
• active zero-length dense and gather extents;
• null-D2 rank-3 load masking and store suppression;
• completion-barrier arrival and TENSORCNT release for null D2;
• sub-row, row, and rank-3 plane iteration origins;
• rejection of advancing overlapping-stride layouts;
• acceptance of repeated-origin overlapping-stride layouts; and
• safe non-iterating rank-5 execution.

The complete Gfx1250ExecutionTest.TensorDma* test set and changed-file pre-commit checks pass locally.

Workload status

This PR intentionally does not claim to fix the complete TensileLite reproducer. It removes independently testable descriptor-model discrepancies and gets the workload closer to the unresolved tail-loop semantic question.

Issue tracking

Progress toward #9935.

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[therock-pr-bot]

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[kuhar]

Just a few comments

[kuhar]

We should apply one zero-extent rule consistently to both copy paths. At emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/tensor_dma.h:283, copy_gather_tensor still treats tensor_dims[0] == 0 as unbounded, while the dense path now treats it as empty. A rank-1 gather descriptor with a nonzero tile dimension and valid_indices == 1 parses and passes validation with a zero extent, so it can still copy past the declared tensor extent. Please either apply the empty-extent rule to gather and add a regression, or document why gather uses a different descriptor meaning.

[newling]

I believe all comments have been addressed.

[atgutier]

[MAJOR]
tensor_dma.h:222 — Null D2 is incorrectly rejected instead of being interpreted as a zero-filled
descriptor group

Reasoning: s_null for an optional descriptor group has the same effective value as four zero SGPRs.
For an active rank-three tile, this produces tensor_dims[2] == 0. Under this PR’s corrected empty-
extent behavior, a load should zero-fill the tile, a store should suppress global writes, and an
enabled completion barrier should still arrive. The new check instead throws UnimplementedInst,
aborting those defined behaviors.

Evidence:

• read_sgpr_group(..., allow_null=true) already converts s_null into a zero-filled group at lines
  42–46.

• parse_descriptor() consequently obtains tensor_dims[2] == 0 at line 137.

• Rank remains three because the active tile_dims[2] is independently encoded in D1 and used by
  rank().

• The public LLVM backend lowers all-zero D2/D3 groups to the two-group form whose VADDR2/VADDR3
  encodings are s_null; the selector makes this decision solely from whether those groups are zero.

• The new bounds predicate at lines 331–336 would correctly mask the zero third extent if execution
  reached it.

• The current regression /tmp/pr9936-current/emulation/rocjitsu/tests/gfx1250_sim_test.cpp:3883
  codifies the incorrect exception.

• Because the exception occurs before arrive_atomic_barrier(), an enabled completion barrier would
  also be lost.

Suggested fix: Remove d2_present and the presence-based rejection. Replace
TensorDmaRankThreeRejectsNullD2Operand with decoded-instruction regressions verifying:

1. A load with an active third tile dimension and null D2/D3 zero-fills LDS.
2. The corresponding store leaves global memory unchanged.
3. An enabled completion barrier still arrives.
4. TENSORCNT is released normally.

Confidence: high.

[newling]

Addressed atgutier’s major review in 459c14fe8f. Optional null D2/D3 groups now retain their architectural zero-filled value; the synthetic presence flag and exception are removed. The decoded rank-3 regression verifies load zero-fill, store suppression, completion-barrier arrival, and normal TENSORCNT release. The other review fixes remain intact, the two-commit stack is rebased onto current develop, all 20 Gfx1250ExecutionTest.TensorDma* tests pass locally, and all review threads are resolved. Fresh CI is running; I will request final re-review after the complete run is green.

[kuhar]

Left 3 inline comments

[newling]

Just to be transparent: my last comment here was pushed by an agent without my knowing. Apologies for the noise, I try not to let them write to network without my explicit permission. I'm still iterating on this PR...

[kuhar]

This doesn't build for me with gcc 13:

In function ‘constexpr void std::__final_insertion_sort(_RandomAccessIterator, _RandomAccessIterator, _Compare) [with _RandomAccessIterator = rocjitsu::amdgpu::tensor_dma_detail::TensorDmaAxis*; _Compare = __gnu_cxx::__ops::_Iter_comp_iter<rocjitsu::amdgpu::tensor_dma_detail::TensorDmaLayout::TensorDmaLayout(const rocjitsu::amdgpu::tensor_dma_detail::TensorDmaDescriptor&)::<lambda(const rocjitsu::amdgpu::tensor_dma_detail::TensorDmaAxis&, const rocjitsu::amdgpu::tensor_dma_detail::TensorDmaAxis&)> >]’,
    inlined from ‘constexpr void std::__sort(_RandomAccessIterator, _RandomAccessIterator, _Compare) [with _RandomAccessIterator = rocjitsu::amdgpu::tensor_dma_detail::TensorDmaAxis*; _Compare = __gnu_cxx::__ops::_Iter_comp_iter<rocjitsu::amdgpu::tensor_dma_detail::TensorDmaLayout::TensorDmaLayout(const rocjitsu::amdgpu::tensor_dma_detail::TensorDmaDescriptor&)::<lambda(const rocjitsu::amdgpu::tensor_dma_detail::TensorDmaAxis&, const rocjitsu::amdgpu::tensor_dma_detail::TensorDmaAxis&)> >]’ at /usr/include/c++/13/bits/stl_algo.h:1950:31,
    inlined from ‘constexpr void std::sort(_RAIter, _RAIter, _Compare) [with _RAIter = rocjitsu::amdgpu::tensor_dma_detail::TensorDmaAxis*; _Compare = rocjitsu::amdgpu::tensor_dma_detail::TensorDmaLayout::TensorDmaLayout(const rocjitsu::amdgpu::tensor_dma_detail::TensorDmaDescriptor&)::<lambda(const rocjitsu::amdgpu::tensor_dma_detail::TensorDmaAxis&, const rocjitsu::amdgpu::tensor_dma_detail::TensorDmaAxis&)>]’ at /usr/include/c++/13/bits/stl_algo.h:4894:18,
    inlined from ‘rocjitsu::amdgpu::tensor_dma_detail::TensorDmaLayout::TensorDmaLayout(const rocjitsu::amdgpu::tensor_dma_detail::TensorDmaDescriptor&)’ at ../rocm-systems/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/tensor_dma.h:209:14,
    inlined from ‘void rocjitsu::amdgpu::tensor_dma_detail::copy_tensor(const TensorDmaDescriptor&, rocjitsu::amdgpu::Wavefront&, bool)’ at ../rocm-systems/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/tensor_dma.h:381:36:
/usr/include/c++/13/bits/stl_algo.h:1859:32: error: array subscript 16 is outside array bounds of ‘const rocjitsu::amdgpu::tensor_dma_detail::TensorDmaLayout [1]’ [-Werror=array-bounds=]
 1859 |           std::__insertion_sort(__first, __first + int(_S_threshold), __comp);
      |           ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from ../rocm-systems/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vimage_exec.cpp:9:
../rocm-systems/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/tensor_dma.h: In function ‘void rocjitsu::amdgpu::tensor_dma_detail::copy_tensor(const TensorDmaDescriptor&, rocjitsu::amdgpu::Wavefront&, bool)’:
../rocm-systems/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/tensor_dma.h:381:25: note: at offset 256 into object ‘layout’ of size 96
  381 |   const TensorDmaLayout layout(desc);
      |                         ^~~~~~
cc1plus: all warnings being treated as errors

[newling]

Marking all review comments as done, I'll follow up on the docs related comments later.