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[rocjitsu] Replace decoder exceptions with results - #10368
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Instruction rejection is normal decoder control flow, so represent it explicitly instead of throwing. Generated decoders now return DecodeResult, diagnostics travel through the failure path, and decoder, operand, translation, patching, fuzz, test, and tool callers handle the result directly. The generator remains the source of truth and all architecture outputs are regenerated. Build on the prerequisite Result and diagnostic utilities. Keep validation call sites uniform without emitting empty per-format methods: IsaInstruction supplies a static constexpr success fallback, while formats hide it only when they have real checks. Generated validation temporaries spell out Result, with no virtual dispatch. Add a valid-dominated large-object decode benchmark. Against the exception-based baseline, the final niche-backed implementation is 4.1% faster on successful decodes and 34.0x faster when rejecting invalid encodings, based on medians from nine interleaved CPU-pinned runs with identical checksums and no unexpected accepts or rejects.
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atgutier
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Instruction rejection is normal decoder control flow, so represent it explicitly instead of throwing. Generated decoders now return DecodeResult, diagnostics travel through the failure path, and decoder, operand, translation, patching, fuzz, test, and tool callers handle the result directly. The generator remains the source of truth and all architecture outputs are regenerated. Build on the prerequisite Result and diagnostic utilities. Keep validation call sites uniform without emitting empty per-format methods: IsaInstruction supplies a static constexpr success fallback, while formats hide it only when they have real checks. Generated validation temporaries spell out Result, with no virtual dispatch. Add a valid-dominated large-object decode benchmark. Against the exception-based baseline, the final niche-backed implementation is 4.1% faster on successful decodes and 34.0x faster when rejecting invalid encodings, based on medians from nine interleaved CPU-pinned runs with identical checksums and no unexpected accepts or rejects. (cherry picked from commit bea7ac8)
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atgutier
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…t calls (#10444) ## Motivation hipTensor and rocThrust gfx1250 objects are refused at code-object load time with "indirect branch or call target recovery is not implemented for relocated kernel text" on `s_swap_pc_i64`. A refused object leaves HIP holding an invalid kernel handle, so the failure surfaces as a segfault rather than a diagnostic. The fix is upstream as #10376; this backports it to `release/bkc/therock-10.1-20260811`. ## Commits Cherry-Picked | # | Upstream | PR | Backport | Subject | |---|----------|-----|----------|---------| | 1 | `b6d838028e` | #10197 | `846fb16d12` | [rocjitsu][docs] Refresh architecture support documentation | | 2 | `5c8e33e391` | #10200 | `db5c58b1be` | [rocjitsu] Define standalone decoder ownership | | 3 | `be1f91998f` | #10199 | `ed102baf1c` | [rocjitsu] Apply async IOFFSET to LDS addresses | | 4 | `fda635e5b4` | — | `ad32ff7c18` | [rocjitsu] Extract per-scope rollback and object-level checks from translate() | | 5 | `8f75eb781e` | — | `4c0cb05207` | [rocjitsu] Emit leading V_NOPs ahead of a gfx1250 MODE write | | 6 | `00aa1e260f` | #9941 | `ded43b1787` | fix(rocjitsu): disable zero-count TDM descriptors | | 7 | `c810647609` | #10192 | `50ca7f1732` | [rocjitsu] Apply MUBUF LDS-load instruction offset to the LDS address | | 8 | `1d7866269d` | #9560 | `2e6bf26943` | [rocjitsu] code rewrite condition validator | | 9 | `95b6c410bb` | #10175 | `8418901076` | [rocjitsu] Fix ds_read_b64_tr_b16 lane layout in gfx950 simulator | | 10 | `bfaebcfb5c` | #10240 | `c4eac1e1f7` | [rocjitsu][util] Add result and diagnostic utilities | | 11 | `dbb7221fa7` | #9775 | `cdd0993a5f` | fix(rocjitsu): route tensor DMA through wave VMID | | 12 | `2779247222` | #9779 | `7bfeba6f5d` | feat(rocjitsu): Lazy vgpr allocation system | | 13 | `a659172a31` | #9936 | `180cf00325` | fix(rocjitsu): honor TDM tensor bounds across iterations | | 14 | `60c29efb39` | #10204 | `370bfb9796` | [rocjitsu] Fix gfx950 decoder extension handling | | 15 | `c1dba564e7` | #10345 | `536110a083` | [rocjitsu] Model gfx1250 wave ABI state | | 16 | `7f71be9f32` | #10346 | `3f922ad5f2` | [rocjitsu] Model gfx1250 barrier synchronization | | 17 | `bea7ac8937` | #10368 | `7b5ecf6c7b` | [rocjitsu] Replace decoder exceptions with results | | 18 | `f2e878694e` | #10371 | `8cf750d23f` | [rocjitsu] Dispatch operand validation by type | | 19 | `dd619bed77` | #9735 | `1a612c47c0` | fix(rocjitsu): respect same-wave LDS ordering | | 20 | `c5fae8d2b2` | #10137 | `4360c4b978` | [rocjitsu] Rename gfx1250 to cdna5 for enums, configs, amdisa codegen helpers and generated symbols. (NFC) | | 21 | `b05a587f89` | #10274 | `bfb5f9fab0` | [rocjitsu] Align CDNA4 MI350X configs with captured topology | | 22 | `f81f9d40db` | #10362 | `8177b5725c` | feat(rocjitsu): cdna5 OOB behavior implementation | | 23 | `53a939bd00` | #10283 | `141b109432` | [rocjitsu] add per-XCD workgroup dispatch observability | | 24 | `a0fb11bc17` | #10414 | `6bb4c5a959` | [rocjitsu] Refactor test encoding handling in execution tests (NFC) | | 25 | `e5109e315e` | #9844 | `322ac26b44` | feat(emulation): debug emulated GPU kernels with real ROCgdb | | 26 | `efa24f23c9` | — | `c3c9641073` | rocjitsu: Point the XCD distribution test at the config that exists | | 27 | `8b7763ef5e` | #10376 | `c3f419555a` | [rocjitsu] Translate gfx1250 lane-banked and kernarg-supplied indirect calls | ## Issue Tracking [ROCM-29436] ## Submission Checklist - [x] Look over the contributing guidelines at https://github.com/ROCm/rocm-systems/blob/develop/CONTRIBUTING.md. [ROCM-29346]: https://amd-hub.atlassian.net/browse/ROCM-29346?atlOrigin=eyJpIjoiNWRkNTljNzYxNjVmNDY3MDlhMDU5Y2ZhYzA5YTRkZjUiLCJwIjoiZ2l0aHViLWNvbS1KU1cifQ [ROCM-29436]: https://amd-hub.atlassian.net/browse/ROCM-29436?atlOrigin=eyJpIjoiNWRkNTljNzYxNjVmNDY3MDlhMDU5Y2ZhYzA5YTRkZjUiLCJwIjoiZ2l0aHViLWNvbS1KU1cifQ --------- Signed-off-by: Tony Gutierrez <anthony.gutierrez@amd.com> Signed-off-by: hanhanW <hanhan0912@gmail.com> Co-authored-by: Jakub Kuderski <jakub@nod-labs.com> Co-authored-by: James Newling <james.newling@gmail.com> Co-authored-by: Fei Kou <feikou@meta.com> Co-authored-by: Austin Lu <austin.lu@amd.com> Co-authored-by: Fei Kou <feikou@anthropic.com> Co-authored-by: Erick Ochoa Lopez <eochoalo@amd.com> Co-authored-by: Han-Chung Wang <hanhan0912@gmail.com> Co-authored-by: Rosa, Ada <arosa@amd.com> Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
cmcknigh
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Aug 25, 2026
Instruction rejection is normal decoder control flow, so represent it explicitly instead of throwing. Generated decoders now return DecodeResult, diagnostics travel through the failure path, and decoder, operand, translation, patching, fuzz, test, and tool callers handle the result directly. The generator remains the source of truth and all architecture outputs are regenerated. Build on the prerequisite Result and diagnostic utilities. Keep validation call sites uniform without emitting empty per-format methods: IsaInstruction supplies a static constexpr success fallback, while formats hide it only when they have real checks. Generated validation temporaries spell out Result, with no virtual dispatch. Add a valid-dominated large-object decode benchmark. Against the exception-based baseline, the final niche-backed implementation is 4.1% faster on successful decodes and 34.0x faster when rejecting invalid encodings, based on medians from nine interleaved CPU-pinned runs with identical checksums and no unexpected accepts or rejects.
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Instruction rejection is normal decoder control flow, so represent it explicitly instead of throwing. Generated decoders now return DecodeResult, diagnostics travel through the failure path, and decoder, operand, translation, patching, fuzz, test, and tool callers handle the result directly. The generator remains the source of truth and all architecture outputs are regenerated.
Build on the prerequisite Result and diagnostic utilities. Keep validation call sites uniform without emitting empty per-format methods: IsaInstruction supplies a static constexpr success fallback, while formats hide it only when they have real checks. Generated validation temporaries spell out Result, with no virtual dispatch.
Add a valid-dominated large-object decode benchmark. Against the exception-based baseline, the final niche-backed implementation is 4.1% faster on successful decodes and 34.0x faster when rejecting invalid encodings, based on medians from nine interleaved CPU-pinned runs with identical checksums and no unexpected accepts or rejects.