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[rocjitsu] Add initial gfx1250 support - #6673
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I split this change into 2 commits: all the 'handwritten' changes and the autogenerated code, so that it's easier to review -- you can select the comment to review in the Files Changed tab. |
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Still have a few things I need to look through and make sure I understand, but there is at least one critical issue (fma) that I think needs to be addressed, so I'll share this now before I have to sign off. Will do another pass tomorrow.
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Rebased on top of #6657 |
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LGTM. Please address my comments (here or in a future PR) if you can.
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only think is don't forget to add the isa xml to the https://github.com/ROCm/rocm-systems/tree/develop/shared/machine-readable-isa when it's allowed |
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The CDNA5 descriptor tests in triton-lang/triton#12512 pass on hardware but fail under Rocjitsu. Crossing raw B128 accesses load and store one extra DWORD near NUM_RECORDS. - CDNA5 buffer bounds (PR #10362, f81f9d4): retain complete accesses, including exact fits, and apply the PR's stated end + 4 <= NUM_RECORDS rule to crossing raw vector accesses. Keep SOFFSET in the check and preserve structured and independent stride bounds. - GFX12 atomic returns (PR #7336, 3a4e98a): test TH[0] independently of the non-temporal and cascade bits. Returning modes 3, 5 and 7 otherwise omit the old value and select non-returning metadata and wait counters. - Signed scratch operands (CDNA5 PR #6673, f6aec50; RDNA4 PR #5053, ca4b97e): sign-extend scalar and vector offsets before combining them and before CDNA5 payload scaling. Compensated negative operands otherwise become large positive private offsets and fault. - CDNA GLOBAL operands (PR #5512, 5a107ce): zero-extend the 32-bit VGPR offset when a scalar base is present. High-bit offsets otherwise resolve four GiB below the intended address. Preserve absolute VGPR pairs and CDNA5 signed addressing. CDNA1-4 manuals and LLVM agree on the unsigned rule. For buffer bounds, the Triton PR measures aligned B128 crossings with four or eight bytes remaining. Other widths and byte-granular bounds follow its stated rule as a model choice pending gfx1250 qualification. Record that limit beside the implementation and regression expectations. Cover bounds, inactive lanes, signed and unsigned operand combinations, atomic writeback and wait counters, including image metadata. Validate 49 Gluon cases with matching ISA and 172 hardware comparisons each on gfx1201 and gfx1100. Audit gfx942/gfx950 buffer, scratch and atomic contracts against the manuals. The standard CTest sweep retains the same 31 baseline failures.
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The CDNA5 descriptor tests in triton-lang/triton#12512 pass on hardware but fail under Rocjitsu. Crossing raw B128 accesses load and store one extra DWORD near NUM_RECORDS. - CDNA5 buffer bounds (PR #10362, f81f9d4): retain complete accesses, including exact fits, and apply the PR's stated end + 4 <= NUM_RECORDS rule to crossing raw vector accesses. Keep SOFFSET in the check and preserve structured and independent stride bounds. - GFX12 atomic returns (PR #7336, 3a4e98a): test TH[0] independently of the non-temporal and cascade bits. Returning modes 3, 5 and 7 otherwise omit the old value and select non-returning metadata and wait counters. - Signed scratch operands (CDNA5 PR #6673, f6aec50; RDNA4 PR #5053, ca4b97e): sign-extend scalar and vector offsets before combining them and before CDNA5 payload scaling. Compensated negative operands otherwise become large positive private offsets and fault. - CDNA GLOBAL operands (PR #5512, 5a107ce): zero-extend the 32-bit VGPR offset when a scalar base is present. High-bit offsets otherwise resolve four GiB below the intended address. Preserve absolute VGPR pairs and CDNA5 signed addressing. CDNA1-4 manuals and LLVM agree on the unsigned rule. For buffer bounds, the Triton PR measures aligned B128 crossings with four or eight bytes remaining. Other widths and byte-granular bounds follow its stated rule as a model choice pending gfx1250 qualification. Record that limit beside the implementation and regression expectations. Cover bounds, inactive lanes, signed and unsigned operand combinations, atomic writeback and wait counters, including image metadata. Validate 49 Gluon cases with matching ISA and 172 hardware comparisons each on gfx1201 and gfx1100. Audit gfx942/gfx950 buffer, scratch and atomic contracts against the manuals. The standard CTest sweep retains the same 31 baseline failures.
kuhar
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The CDNA5 descriptor tests in triton-lang/triton#12512 pass on hardware but fail under Rocjitsu. Crossing raw B128 accesses load and store one extra DWORD near NUM_RECORDS. - CDNA5 buffer bounds (PR #10362, f81f9d4): retain complete accesses, including exact fits, and apply the PR's stated end + 4 <= NUM_RECORDS rule to crossing raw vector accesses. Keep SOFFSET in the check and preserve structured and independent stride bounds. - GFX12 atomic returns (PR #7336, 3a4e98a): test TH[0] independently of the non-temporal and cascade bits. Returning modes 3, 5 and 7 otherwise omit the old value and select non-returning metadata and wait counters. - Signed scratch operands (CDNA5 PR #6673, f6aec50; RDNA4 PR #5053, ca4b97e): sign-extend scalar and vector offsets before combining them and before CDNA5 payload scaling. Compensated negative operands otherwise become large positive private offsets and fault. - CDNA GLOBAL operands (PR #5512, 5a107ce): zero-extend the 32-bit VGPR offset when a scalar base is present. High-bit offsets otherwise resolve four GiB below the intended address. Preserve absolute VGPR pairs and CDNA5 signed addressing. CDNA1-4 manuals and LLVM agree on the unsigned rule. - PC exports and targets (import handling #9844, e5109e3): apply the architecture's extension rule to GETPC, CALL and SWAPPC return addresses. RDNA4 zero-extends 48 bits; older targets sign-extend 48 bits and CDNA5 sign-extends 57 bits. Keep imported PCs as raw 48/57-bit addresses for instruction fetch, consistent with RFE, and preserve all CDNA5 target bits. Limit the positive linked-rel32 tag to 48-bit targets. Remove the negative tag on every target: it aliases ordinary sign-filled PC exports. Both forms otherwise corrupt valid 57-bit targets or older high-PC round trips when a load bias is present. For buffer bounds, the Triton PR measures aligned B128 crossings with four or eight bytes remaining. Other widths and byte-granular bounds follow its stated rule as a model choice pending gfx1250 qualification. Record that limit beside the implementation and regression expectations. Cover bounds, inactive lanes, signed and unsigned operand combinations, atomic writeback and wait counters, including image metadata. Validate 49 Gluon cases with matching ISA and 172 hardware comparisons each on gfx1201 and gfx1100. Audit gfx942/gfx950 buffer, scratch and atomic contracts against the manuals. The standard CTest sweep retains the same 31 baseline failures. Decode and execute PC regression cases on gfx1100, gfx1201, gfx950 and gfx1250, including high address bits, next-PC boundaries and operand aliasing. Follow SETPC/SWAPPC through real page tables to fetch a high mapped destination, including both relocation-tag collisions with a nonzero load bias. Older linked-rel32 debugger coverage is retained. These are manual/LLVM-backed simulation checks without physical high-address PC qualification. RDNA3/3.5 sign-filled exports follow LLVM against conflicting manual tables; record that choice beside the generator and test oracle. Add explicit test braces for GCC.
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The CDNA5 descriptor tests in triton-lang/triton#12512 pass on hardware but fail under Rocjitsu. Crossing raw B128 accesses load and store one extra DWORD near NUM_RECORDS. - CDNA5 buffer bounds (PR #10362, f81f9d4): retain complete accesses, including exact fits, and apply the PR's stated end + 4 <= NUM_RECORDS rule to crossing raw vector accesses. Keep SOFFSET in the check and preserve structured and independent stride bounds. - GFX12 atomic returns (PR #7336, 3a4e98a): test TH[0] independently of the non-temporal and cascade bits. Returning modes 3, 5 and 7 otherwise omit the old value and select non-returning metadata and wait counters. - Signed scratch operands (CDNA5 PR #6673, f6aec50; RDNA4 PR #5053, ca4b97e): sign-extend scalar and vector offsets before combining them and before CDNA5 payload scaling. Compensated negative operands otherwise become large positive private offsets and fault. - CDNA GLOBAL operands (PR #5512, 5a107ce): zero-extend the 32-bit VGPR offset when a scalar base is present. High-bit offsets otherwise resolve four GiB below the intended address. Preserve absolute VGPR pairs and CDNA5 signed addressing. CDNA1-4 manuals and LLVM agree on the unsigned rule. - PC exports and targets (import handling #9844, e5109e3): apply the architecture's extension rule to GETPC, CALL and SWAPPC return addresses. RDNA4 zero-extends 48 bits; older targets sign-extend 48 bits and CDNA5 sign-extends 57 bits. Keep imported PCs as raw 48/57-bit addresses for instruction fetch, consistent with RFE, and preserve all CDNA5 target bits. Limit the positive linked-rel32 tag to 48-bit targets. Remove the negative tag on every target: it aliases ordinary sign-filled PC exports. Both forms otherwise corrupt valid 57-bit targets or older high-PC round trips when a load bias is present. For buffer bounds, the Triton PR measures aligned B128 crossings with four or eight bytes remaining. Other widths and byte-granular bounds follow its stated rule as a model choice pending gfx1250 qualification. Record that limit beside the implementation and regression expectations. Cover bounds, inactive lanes, signed and unsigned operand combinations, atomic writeback and wait counters, including image metadata. Validate 49 Gluon cases with matching ISA and 172 hardware comparisons each on gfx1201 and gfx1100. Audit gfx942/gfx950 buffer, scratch and atomic contracts against the manuals. The standard CTest sweep retains the same 31 baseline failures. Decode and execute PC regression cases on gfx1100, gfx1201, gfx950 and gfx1250, including high address bits, next-PC boundaries and operand aliasing. Follow SETPC/SWAPPC through real page tables to fetch a high mapped destination, including both relocation-tag collisions with a nonzero load bias. Older linked-rel32 debugger coverage is retained. These are manual/LLVM-backed simulation checks without physical high-address PC qualification. RDNA3/3.5 sign-filled exports follow LLVM against conflicting manual tables; record that choice beside the generator and test oracle. Add explicit test braces for GCC.
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…14352) The CDNA5 descriptor tests in [triton-lang/triton#12512](triton-lang/triton#12512) pass on hardware but fail under Rocjitsu. Crossing raw B128 accesses load and store one extra DWORD near `NUM_RECORDS`. Auditing neighboring instructions and extension rules across gfx942/gfx950, gfx1100/gfx1201 and gfx1250 exposed further address and return defects. - **CDNA5 buffer bounds** (introduced by #10362, `f81f9d40db67`): keep complete accesses, including exact fits, and apply the Triton PR's stated `end + 4 <= NUM_RECORDS` rule to crossing raw vector accesses. Count `SOFFSET` and preserve structured and independent stride checks. - **GFX12 atomic returns** (introduced by #7336, `3a4e98a167e6`): test `TH[0]` independently of the non-temporal and cascade bits. Return modes 3, 5 and 7 otherwise omit the old value and select non-returning metadata and wait counters. - **GFX12 scratch operands** (CDNA5 #6673, `f6aec5064565`; RDNA4 #5053, `ca4b97ef2cc6`): sign-extend scalar/vector inputs before combining them and before CDNA5 payload scaling. Compensated negative inputs otherwise become large positive private offsets and fault. - **CDNA1–4 GLOBAL operands** (introduced by #5512, `5a107cebd601`): zero-extend the 32-bit VGPR offset when a scalar base is present. High-bit offsets otherwise address four GiB below the intended location. Preserve absolute VGPR pairs and the separate CDNA5 signed rule. - **PC extension and width**: GETPC, CALL and SWAPPC now export signed 48-bit PCs on older targets, zero-filled 48-bit PCs on RDNA4, and signed 57-bit PCs on CDNA5. SETPC/SWAPPC use raw masked 48/57-bit internal addresses so high targets remain fetchable through page tables. CDNA5 keeps all 57 target bits and bypasses linked-rel32 tags. The ambiguous negative tag is removed on every target so sign-filled PC exports round-trip with a load bias; 48-bit targets retain the positive tag covered by gfx950 debugger integration. Previously high PCs exposed the wrong upper bits or lost valid target bits. The generator and its 40 emitted PC handlers agree. RDNA3/3.5 sign-filled exports follow LLVM against conflicting manual tables; high-address PC behavior has no physical qualification. The gfx1250 buffer evidence covers aligned B128 crossings with four/eight bytes remaining. Other widths and byte-granular bounds follow the Triton PR's stated rule as model choices pending gfx1250 hardware qualification; the source and tests say so explicitly. The gfx942/gfx950 manual audit preserves the existing legacy scratch policy where no legal allocated-input mismatch was demonstrated. Local validation: - 49 Gluon cases pass through matching descriptor/instruction ISA. The installed Triton predates the new descriptor frontend API, so this is an ISA-equivalent replay, not a rebuild of that API. - 172 saved physical gfx1201 comparisons and 172 physical gfx1100 comparisons match simulation: buffer bounds, atomic return controls, legal scratch operands and GLOBAL offsets. The buffer-clamp rule remains CDNA5-specific. - gfx942 and gfx950 buffer/atomic/scratch/GLOBAL contracts were checked against their manuals and LLVM. All eight compiled HIP GLOBAL load/store simulation cases pass; no physical gfx942/gfx950 qualification is claimed. - 28 PC test groups cover gfx1100/gfx1201/gfx950/gfx1250, including next-PC boundaries, target width and SWAPPC operand aliasing. The original handlers fail 11 of the initial 16 groups. Page-table-backed fetch and nonzero-load-bias tests also reproduce the additional import/relocation gaps; all 28 final PC groups pass, including GETPC-to-SETPC/SWAPPC round trips with a nonzero load bias. Encodings were independently verified with LLVM. Four groups execute the destination through real page tables, including both 57-bit relocation-tag collisions. These are source-backed simulation checks without physical high-address PC qualification. - After rebasing onto current `develop`, the project builds and all 2,851 generator checks pass, with 46 skipped. Earlier GCC syntax checks cover the atomic and PC test translation units with `-Werror=dangling-else`; explicit braces fix the reported CI build error. Changed-file formatting hooks pass. - Rebase validation passes all 313 focused CTests, including PC, address, atomic and newly landed fork/join coverage. Standard CTest retains exactly the same 31 baseline failure names and classifications: 31/9181 after rebasing versus 31/9010 before rebasing. No new failure names.
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…14352) The CDNA5 descriptor tests in [triton-lang/triton#12512](triton-lang/triton#12512) pass on hardware but fail under Rocjitsu. Crossing raw B128 accesses load and store one extra DWORD near `NUM_RECORDS`. Auditing neighboring instructions and extension rules across gfx942/gfx950, gfx1100/gfx1201 and gfx1250 exposed further address and return defects. - **CDNA5 buffer bounds** (introduced by #10362, `f81f9d40db67`): keep complete accesses, including exact fits, and apply the Triton PR's stated `end + 4 <= NUM_RECORDS` rule to crossing raw vector accesses. Count `SOFFSET` and preserve structured and independent stride checks. - **GFX12 atomic returns** (introduced by #7336, `3a4e98a167e6`): test `TH[0]` independently of the non-temporal and cascade bits. Return modes 3, 5 and 7 otherwise omit the old value and select non-returning metadata and wait counters. - **GFX12 scratch operands** (CDNA5 #6673, `f6aec5064565`; RDNA4 #5053, `ca4b97ef2cc6`): sign-extend scalar/vector inputs before combining them and before CDNA5 payload scaling. Compensated negative inputs otherwise become large positive private offsets and fault. - **CDNA1–4 GLOBAL operands** (introduced by #5512, `5a107cebd601`): zero-extend the 32-bit VGPR offset when a scalar base is present. High-bit offsets otherwise address four GiB below the intended location. Preserve absolute VGPR pairs and the separate CDNA5 signed rule. - **PC extension and width**: GETPC, CALL and SWAPPC now export signed 48-bit PCs on older targets, zero-filled 48-bit PCs on RDNA4, and signed 57-bit PCs on CDNA5. SETPC/SWAPPC use raw masked 48/57-bit internal addresses so high targets remain fetchable through page tables. CDNA5 keeps all 57 target bits and bypasses linked-rel32 tags. The ambiguous negative tag is removed on every target so sign-filled PC exports round-trip with a load bias; 48-bit targets retain the positive tag covered by gfx950 debugger integration. Previously high PCs exposed the wrong upper bits or lost valid target bits. The generator and its 40 emitted PC handlers agree. RDNA3/3.5 sign-filled exports follow LLVM against conflicting manual tables; high-address PC behavior has no physical qualification. The gfx1250 buffer evidence covers aligned B128 crossings with four/eight bytes remaining. Other widths and byte-granular bounds follow the Triton PR's stated rule as model choices pending gfx1250 hardware qualification; the source and tests say so explicitly. The gfx942/gfx950 manual audit preserves the existing legacy scratch policy where no legal allocated-input mismatch was demonstrated. Local validation: - 49 Gluon cases pass through matching descriptor/instruction ISA. The installed Triton predates the new descriptor frontend API, so this is an ISA-equivalent replay, not a rebuild of that API. - 172 saved physical gfx1201 comparisons and 172 physical gfx1100 comparisons match simulation: buffer bounds, atomic return controls, legal scratch operands and GLOBAL offsets. The buffer-clamp rule remains CDNA5-specific. - gfx942 and gfx950 buffer/atomic/scratch/GLOBAL contracts were checked against their manuals and LLVM. All eight compiled HIP GLOBAL load/store simulation cases pass; no physical gfx942/gfx950 qualification is claimed. - 28 PC test groups cover gfx1100/gfx1201/gfx950/gfx1250, including next-PC boundaries, target width and SWAPPC operand aliasing. The original handlers fail 11 of the initial 16 groups. Page-table-backed fetch and nonzero-load-bias tests also reproduce the additional import/relocation gaps; all 28 final PC groups pass, including GETPC-to-SETPC/SWAPPC round trips with a nonzero load bias. Encodings were independently verified with LLVM. Four groups execute the destination through real page tables, including both 57-bit relocation-tag collisions. These are source-backed simulation checks without physical high-address PC qualification. - After rebasing onto current `develop`, the project builds and all 2,851 generator checks pass, with 46 skipped. Earlier GCC syntax checks cover the atomic and PC test translation units with `-Werror=dangling-else`; explicit braces fix the reported CI build error. Changed-file formatting hooks pass. - Rebase validation passes all 313 focused CTests, including PC, address, atomic and newly landed fork/join coverage. Standard CTest retains exactly the same 31 baseline failure names and classifications: 31/9181 after rebasing versus 31/9010 before rebasing. No new failure names.
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Motivation
Add Rocjitsu support for AMDGPU
gfx1250code objects so local decode, execution, and DBTvalidation can cover kernels produced by the gfx1250 compiler path.
gfx1250 brings new decode and execution details that need explicit support, including high-VGPR
bank selection, gfx1250 matrix formats, SWMMAC modifiers, tensor DMA descriptors, transpose-load
layouts, and 64-bit literal forms.
Technical Details
Target plumbing. Added
gfx1250architecture and target IDs, code-object machine flag/offload-triplemapping, a gfx1250 VM config, decoder factory wiring, and tests for public enum stability and target
selection. The included VM config is a placeholder seeded from the existing CDNA4 config, retaining
the CDNA4-style XCD/IOD and memory-width shape while adjusting the target identity, wave size, and
register allocation for gfx1250 bring-up and validation.
Generator/profile support. Added a gfx1250 ISA profile for the XML schema and code generation rules.
The profile gated gfx1250-only behavior such as 64-bit literals, VGPR-MSB operand resolution, VOPD
generation, matrix-format operand sizing, and source splitting for large generated VOP3/VOPC files.
VGPR high-bank indexing. Added wavefront MODE state and helpers for the
S_SET_VGPR_MSBlayout.Generated operands resolved src0/src1/src2/dst through the role-specific high-bank selector while
non-gfx1250 targets kept the existing v0-v255 addressing path.
Launch setup. Extended command-processor initialization for gfx1250 launch state, including TTMP
workgroup ID payloads, 2D/3D grid decomposition, and enough scalar slots for TTMP-backed launch
registers.
Matrix execution. Renamed the shared matrix helper around MMA because it handled both MFMA and
WMMA-style operations. gfx1250 generation handled WMMA/SWMMAC decode, matrix-format operand sizes,
index-key/reuse/sign/clamp modifiers, and accumulator-style destination behavior.
Tensor DMA and transpose loads. Added shared helpers for tensor DMA descriptor parsing and the
descriptor forms covered by the current corpus: global/LDS copies, padding, iteration, barriers,
dense descriptors, and gather descriptors. Added cross-lane transpose helpers for TR_B4, TR_B6,
TR_B8, and TR_B16 layouts.
Generated ISA. Regenerated the gfx1250 ISA sources from the XML spec under
lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250.Coverage gaps. This does not claim exhaustive execution coverage for every instruction in the
gfx1250 XML. Follow-up coverage is still needed for broader tensor DMA combinations, the full
WMMA/SWMMAC format cross product, image/sample paths, and remaining vector/packed-operation corners.
JIRA ID
Test Plan
Additional validation used a local HIP kernel corpus targeting new gfx1250 instructions and a set of
IREE-generated gfx1250 kernels.
Test Result
57 passed466/466 passedand related gfx1250 paths were exercised through the direct Rocjitsu harness
Submission Checklist