[rocjitsu] Model gfx1250 wave ABI state

emulation/rocjitsu/lib/python/amdisa/codegen/execute/sema_lower.py

@@ -272,12 +272,12 @@ def _vcc_write_stmt(ctx: LoweringContext) -> str:
     if ctx.vcc_dst and ctx.vcc_dst != '__vcc__':
         return _write_vcc_mask_to_explicit_dst(ctx.vcc_dst)
     if ctx.vcc_dst == '__vcc__':
-        return 'wf.set_vcc(vcc);'
+        return 'wf.set_vcc_mask(vcc);'
     if ctx.operand_map:
         dst = ctx.operand_map.dst(0)
         if dst:
             return _write_vcc_mask_to_explicit_dst(dst.name)
-    return 'wf.set_vcc(vcc);'
+    return 'wf.set_vcc_mask(vcc);'
 
 
 def _indent(ctx: LoweringContext) -> str:

emulation/rocjitsu/lib/python/amdisa/codegen/execute/vector_cmp.py

@@ -163,12 +163,12 @@ def gen_vector_cmp_class(
     L.append('  }')
     if is_cmpx:
         if cmpx_writes_vcc:
-            L.append('  wf.set_vcc(result);')
+            L.append('  wf.set_vcc_mask(result);')
         L.append('  wf.set_exec(result);')
     elif dst:
         L.extend(_write_explicit_lane_mask(dst[0], 'vcc'))
     else:
-        L.append('  wf.set_vcc(vcc);')
+        L.append('  wf.set_vcc_mask(vcc);')
     return '\n'.join(L)
 
 
@@ -372,7 +372,7 @@ def gen_vector_cmp(
         L.extend(_write_explicit_lane_mask(dst[0], 'vcc'))
     else:
         # VOPC: write to VCC.
-        L.append('  wf.set_vcc(vcc);')
+        L.append('  wf.set_vcc_mask(vcc);')
     return '\n'.join(L)
 
 
@@ -412,7 +412,7 @@ def gen_vector_cmpx(
         if dst and is_vop3:
             L.extend(_write_explicit_lane_mask(dst[0], 'result'))
         else:
-            L.append('  wf.set_vcc(result);')
+            L.append('  wf.set_vcc_mask(result);')
     L.append('  wf.set_exec(result);')
     return '\n'.join(L)
 
@@ -498,5 +498,5 @@ def gen_vector_add_co(
         # VOP3_SDST_ENC: carry-out goes to sdst (any SGPR pair).
         L.extend(_write_explicit_lane_mask(dst[1], 'vcc'))
     else:
-        L.append('  wf.set_vcc(vcc);')
+        L.append('  wf.set_vcc_mask(vcc);')
     return '\n'.join(L)

emulation/rocjitsu/lib/python/amdisa/codegen/execute/vector_special.py

@@ -586,7 +586,7 @@ def gen_vector_div_scale(
     if len(dst) > 1:
         L.append(f'  amdgpu::write_wave_mask_scalar({dst[1]}, wf, vcc);')
     else:
-        L.append('  wf.set_vcc(vcc);')
+        L.append('  wf.set_vcc_mask(vcc);')
     return '\n'.join(L)
 
 

emulation/rocjitsu/lib/python/amdisa/tests/test_gen_vector_cmpx.py

@@ -101,7 +101,7 @@ def _make_codegen(profile) -> CodeGenerator:
 
 # Regex tolerant to whitespace and identifier choice. We anchor on the
 # stable parts of the contract — the wave-mask helper calls
-# ``set_vcc``, ``set_exec``) and the dst identifier — not on the exact
+# ``set_vcc_mask``, ``set_exec``) and the dst identifier — not on the exact
 # variable name of the result-mask local.
 def _re_write_wave_mask(dst_ident: str) -> re.Pattern[str]:
     return re.compile(
@@ -110,7 +110,7 @@ def _re_write_wave_mask(dst_ident: str) -> re.Pattern[str]:
     )
 
 
-_RE_SET_VCC = re.compile(r'\bwf\s*\.\s*set_vcc\s*\(\s*\w+\s*\)\s*;')
+_RE_SET_VCC = re.compile(r'\bwf\s*\.\s*set_vcc_mask\s*\(\s*\w+\s*\)\s*;')
 _RE_SET_EXEC = re.compile(r'\bwf\s*\.\s*set_exec\s*\(\s*\w+\s*\)\s*;')
 _RE_ANY_WRITE_WAVE_MASK = re.compile(r'\bamdgpu::write_wave_mask_scalar\s*\(')
 
@@ -147,7 +147,7 @@ class TestGenVectorCmpxWriteBacks:
       * ``set_exec`` is emitted unconditionally.
       * a wave-size-width-aware write on the SDST is emitted iff
         ``profile.cmpx_writes_vcc and is_vop3 and dst``.
-      * ``set_vcc`` is emitted iff
+      * ``set_vcc_mask`` is emitted iff
         ``profile.cmpx_writes_vcc and not (is_vop3 and dst)``.
 
     The ``op='t'`` shortcut is intentional: it bypasses ``_cmp_condition``
@@ -200,11 +200,11 @@ def test_writeback_invariants(
         # VCC write: must appear iff expected.
         vcc_match = _RE_SET_VCC.search(body)
         if expect_vcc_write:
-            assert vcc_match, f'Expected wf.set_vcc(...) call; body was:\n{body}'
+            assert vcc_match, f'Expected wf.set_vcc_mask(...) call; body was:\n{body}'
         else:
             assert (
                 not vcc_match
-            ), f'Did not expect wf.set_vcc(...) call; body was:\n{body}'
+            ), f'Did not expect wf.set_vcc_mask(...) call; body was:\n{body}'
 
         # Mutual exclusion: a single V_CMPX never writes both VCC and SDST.
         assert not (

emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop3_exec.cpp

@@ -2903,7 +2903,7 @@ void VCmpxClassF32Vop3::execute_impl(amdgpu::Wavefront &wf) {
     if (match)
       result |= (1ULL << lane);
   }
-  wf.set_vcc(result);
+  wf.set_vcc_mask(result);
   wf.set_exec(result);
 }
 
@@ -2951,7 +2951,7 @@ void VCmpxClassF64Vop3::execute_impl(amdgpu::Wavefront &wf) {
     if (match)
       result |= (1ULL << lane);
   }
-  wf.set_vcc(result);
+  wf.set_vcc_mask(result);
   wf.set_exec(result);
 }
 
@@ -3076,7 +3076,7 @@ void VCmpxClassF16Vop3::execute_impl(amdgpu::Wavefront &wf) {
     if (match)
       result |= (1ULL << lane);
   }
-  wf.set_vcc(result);
+  wf.set_vcc_mask(result);
   wf.set_exec(result);
 }