[BREAKING][ops, model] refactor: replace OpSlot with VeomniOp by Zx55 · Pull Request #1142 · ByteDance-Seed/VeOmni

Zx55 · 2026-08-31T04:38:21Z

Merge stack

Ops PRs that land before this one, because they change kernels this refactor moves or add kernels on the old OpSlot API. Every other open ops PR rebases onto VeomniOp after this merges, and carries a note pointing here.

Already on main — port into this branch on the next rebase:

[model] feat: add deepseek-v4 NPU kernels #1218 DeepSeek-V4 NPU kernels. Ported in b199a26: cann rows for dsa_indexer / dsa_attention / mhc, and the DeepSeek-V4 NPU patch_gen dispatches through VeomniOp.
[ops, ci] fix: mask padded GDR dot lanes on Ascend #970 Ascend GDR padded-lane NaN mask. Ported in 53d5383 onto gated_delta_rule/vendor/; its regression test moves to tests/ops/gated_delta_rule/.
[parallel, ops] feat: Support Ulysses Sp for Qwen3.8 Flash Next & QSA TileLang GPU #1197 Qwen3.8 Flash Next Ulysses SP + QSA TileLang. Ported in 53d5383: a new qsa_attention op with eager and tilelang rows, and the qwen4_exp patch_gen keeps main's Ulysses logic on instance-local VeomniOps.
[ci] fix: install triton-ascend in the NPU test workflows #1307 Install triton-ascend in the NPU unit and e2e workflows. Ported in b60b81176: install triton==3.2.0, then triton-ascend==3.2.1, and check triton._C.libtriton.ascend.
[ci, ops] feat: cover the Ascend GatedDeltaNet kernels in NPU tests #1309 Ascend GatedDeltaNet NPU coverage. Ported in b60b81176 onto the registry paths. torch_npu rms_norm_gated uses npu_swiglu for SiLU and the eager fp32 gate multiply for sigmoid. Triton causal_conv1d and chunk_gated_delta_rule move a CPU cu_seqlens onto the activation device. The backward autotune key is ['H', 'K', 'V', 'BT']. The new tests call resolve_op. NPU training defaults and the Qwen4-Exp e2e smoke use torch_npu / triton, with SP=2.
[dist, parallel] refactor: remove the Ulysses group override #1311 Remove the Ulysses sequence-parallel group override. Merged in 4b21b4c6d. set_ulysses_sequence_parallel_group is gone. SP and CP tests build real states with _init_parallel_state and enter them with use_parallel_state.
[ops] fix: stop NPU GDN Triton kernels recompiling per batch length #1264 Stop NPU GDN Triton kernels recompiling per batch length. Merged in 4140f586c onto vendor/triton/. NT, N, B, and TOTAL_TASKS leave tl.constexpr and join do_not_specialize in chunk_delta_h, chunk_o, chunk_scaled_dot_kkt, and wy_fast.
[ops] fix: causal_conv1d over-counts dh0 when the backward tile is narrower than the conv window #1265 Stop causal_conv1d backward over-counting dh0 when the tile is narrower than the conv window. Merged in 4140f586c. mask_head_rows and the dy0 loads are bounded by T_len. With initial_state, BT is at least next_power_of_2(W), and W > 8 raises. The packed short-segment regression is in tests/ops/gated_delta_rule/test_gated_delta_rule.py and calls the vendored impl, because the registry wrapper still passes initial_state=None. tests/ops/test_npu_kernels.py stays deleted.

Deliberately not in this stack, rebasing onto VeomniOp afterwards instead: #1223 (the sigmoid-vs-npu_swiglu split is already ported from #1309; the remaining device/dtype and invalid-gate contracts edit the deleted npu_rms_norm_gated.py), #966 (910B4-1 BV=64 profile — the root cause has no hardware evidence yet, and it edits files this PR deletes), #1306 (merged-MoE backward activation lifetime — a memory optimization, not a correctness fix), #1199 (expert-parallel numerics — too large to sit in front of the refactor; it changes routing-weight arithmetic for every Triton MoE user), #1200 (compiled-training precision — two of its three code changes are already resolved here, see the note on that PR).

Why

VeOmni previously selected optimized operations through several independent mechanisms, including OpSlot, kernel factories, global function replacement, loss mapping mutation, and attention-specific registries.

This made implementation selection difficult to reason about and prevented different model instances from safely selecting different implementations.

This PR consolidates tensor-level operations under veomni.ops. Models hold instance-local VeomniOp handles. Model-specific argument processing and loss policy remain in veomni.models.

What does this PR do?

The refactor creates one path from implementation registration to instance-local model execution:

flowchart TB
    subgraph Registration["1. Operation registration"]
        direction LR
        Raw["Raw forward/backward pair"]
        Opaque["Opaque eager or vendor wrapper"]
        Register["register_op(...)"]
        Entry["OpEntry<br/>wrapper + optional raw pair"]
        Registry["OP_REGISTRY<br/>(op, variant, implementation, device)"]
        Raw --> Register
        Opaque --> Register
        Register --> Entry
        Entry --> Registry
    end

    subgraph Runtime["2. Model construction and ordinary execution"]
        direction LR
        YAML["model.ops_implementation"]
        Config["OpsImplementationConfig"]
        Model["Model __init__"]
        Handle["VeomniOp(op, variant, impl)"]
        Resolve["Resolve row and<br/>check hardware"]
        Call["entry.wrapper(...)"]
        Kernel["Selected implementation<br/>PyTorch / Liger / Triton / NPU / MLU"]
        YAML --> Config
        Config --> Model
        Model --> Handle
        Handle --> Resolve
        Registry --> Resolve
        Resolve --> Call
        Call --> Kernel
    end

    subgraph Compound["3. Compound operation execution"]
        direction LR
        Outer["Outer raw forward/backward"]
        Inner["resolve_inner_op(...)"]
        RawCall["Call inner raw forward/backward<br/>without nesting an autograd wrapper"]
        State["Flatten and restore SavedState"]
        Outer --> Inner
        Registry --> Inner
        Inner --> RawCall
        RawCall --> State
    end

The important properties are:

One source of truth: tensor-level implementations are registered in OP_REGISTRY, including an explicit eager row.
Instance-local selection: each model constructs its own VeomniOp; constructing one model no longer changes another model's implementation.
Two registration forms: an implementation may provide either a raw forward/backward pair or an opaque eager/vendor wrapper.
Composable autograd: compound operations call inner raw pairs directly and preserve their saved state without nesting Function.apply.
Clear ownership boundary: tensor math lives in veomni.ops; model-specific input adaptation and loss policy live in veomni.models.

Process-wide integration is limited to installation work such as registering VeOmni attention names with Transformers. Attention masks, batch-invariant patches, and model-side loss policy are not registered operation rows.

HF-interface families bind attention from config._attn_implementation. Families that are not on that path (Wan, MiniMax, Flux, Qwen Image, LTX) define no model-local eager_attention_forward, so they bind through resolve_op_impl("attn_implementation", eager_as="veomni_sdpa").

The complete operator catalog and extension guide are documented in veomni/ops/README.md.

Authoring, registration, and modeling usage of VeomniOp / OP_REGISTRY are documented in veomni/ops/README.md and docs/design/op_selection.md.

Config migration

model.ops_implementation.* keeps its field names. Values renamed since main still parse for one transition window. OpsImplementationConfig maps them to the current name and logs a deprecation warning that names the replacement. The table is also in docs/usage/arguments.md.

Field	Value on `main`	Resolves to
`attn_implementation`	`veomni_*_with_sp` (FA2/FA3/FA4, Hub forms, Flex, Magi)	The same name without `_with_sp`. Ulysses now lives inside the adapter.
`moe_implementation`	`fused`	The name `main` resolved it to on that host: `fused_quack` (GPU), `fused_npu` (NPU), `fused_mlu` (MLU with Apex) or `fused_triton` (MLU without Apex).
`moe_implementation`	`fused_mlu_triton`	`fused_triton`
`cross_entropy_loss_implementation`	`npu`	`chunk_loss`. The `main` entry was an alias of `chunk_loss`, not a third-party NPU kernel.
`rms_norm_implementation`, `rotary_pos_emb_implementation`, `rotary_pos_emb_vision_implementation`, `rms_norm_gated_implementation`	`npu`	`torch_npu`
`causal_conv1d_implementation`, `chunk_gated_delta_rule_implementation`	`npu`	`triton`, the vendored Triton-Ascend kernel
`chunk_gated_delta_rule_implementation`	`npu_ascendc`	`fla_npu`

rms_norm_implementation is shared by every RMSNorm variant, so one value is also mapped per variant. unweighted (Flux, LTX-2.3, DeepSeek-V4) has no Ascend kernel, so torch_npu and the old npu both resolve to eager for that variant, because the main row of that name was PyTorch math. Consumers pass resolve_op_impl(field, variant=...), and the mapping is logged once.

rms_norm_implementation='qwen3_5' is rejected at parse time. qwen3_5 was the RMSNorm variant name (now offset), not an implementation value. Other unknown values fail at model build, and the error lists the registered implementations.

Host defaults

The seven general-purpose fields (moe, cross_entropy_loss, rms_norm, swiglu_mlp, rotary_pos_emb, rotary_pos_emb_vision, load_balancing_loss) now default to None, and OpsImplementationConfig fills an unset field with the host default. The filled values are the same as main on GPU, NPU and MLU. The table is in docs/usage/arguments.md.

main treated a value equal to the GPU dataclass default as unset and rewrote it on NPU and MLU, even when the YAML set it explicitly. Explicit values are now never rewritten:

On NPU, an explicit GPU-only value (liger_kernel, fused_triton, or load_balancing_loss_implementation: triton) raises at config validation instead of silently selecting the NPU kernel. GPU YAMLs that pin these keys must drop or replace them for NPU runs
On NPU, an explicit rotary_pos_emb_vision_implementation: eager stays eager. main rewrote it to npu
On MLU, an explicit liger_kernel is kept and fails at model build, where main rewrote it to eager. An explicit fused_triton MoE stays fused_triton even with Apex, where main switched it to fused_mlu

Operator surface differences from `main`

Except for the differences below, the refactored operations are intended to preserve the tensor contracts, numerical behavior, gradients, and hardware support of main. Moving an existing implementation into the new registry is not considered a behavior change.

Area	Difference from `main`	Behavior change
RMSNorm `unweighted`	No Ascend row is registered. `rms_norm_implementation='torch_npu'` (or the old `npu`) resolves to `eager` for this variant, because the previous NPU-labelled path was PyTorch math and did not call a distinct `torch_npu` kernel.	No numerical change; replaces a hardware alias with a variant-scoped config alias.
RMSNorm `deepseek_v4`	New variant for DeepSeek-V4's fp32 affine scale, with rows `deepseek_v4/{eager,liger_kernel,torch_npu}`. `main` routed V4 through `standard`. The `torch_npu` row calls the same `torch_npu.npu_rms_norm` kernel that `main` reached through `standard`.	Eager keeps V4's fp32-affine math. The NPU kernel is unchanged.
RMSNorm `offset`	The `qwen3_5` variant is renamed to `offset`. Rows are `offset/{eager,liger_kernel,torch_npu}`. Consumers are Qwen3.5, Qwen3.5-MoE, Gemma3, and Qwen4-Exp.	Naming only; offset-1 Gemma-style math is unchanged.
RMSNorm `group_size`	Every RMSNorm variant accepts optional `group_size`. Fused weighted rows delegate grouped calls to eager. Only Qwen4-Exp passes a non-`None` value (`hc_norm`, `norm_key`, `norm_query`, `norm_conv`).	Contract extension. Qwen4 grouped math matches `main`'s local reshape; other callers omit it.
Cross-entropy	Exposes `standard/{eager,chunk_loss,liger_kernel}`. The previous `npu` entry was an alias of `chunk_loss`. `npu` now parses as a deprecated config alias of `chunk_loss` on any host. Causal and sequence-classification policy remains model-side.	No kernel-math change; removes a registry alias and separates model policy.
Vision RoPE	There is no separate `rope_vision` family. Rank-3 vision and text full RoPE both use `rope/full`. `rotary_pos_emb_vision_implementation` remains temporarily as an independent configuration choice.	No numerical change; consolidates equivalent tensor operations.
Gated RMSNorm	`rms_norm_gated/standard/{eager,fla,torch_npu}` accept `activation="sigmoid"`, which Qwen4-Exp selects through `output_gate_type`. `torch_npu` fuses SiLU with `npu_swiglu` and uses the eager fp32 gate multiply for sigmoid.	Contract extension. SiLU callers are unchanged.
Qwen4-Exp QSA	`main` dispatches `qsa_attention_implementation` inside the modeling `eager_attention_forward`. Here it is the `qsa_attention/standard/{eager,tilelang}` op, which takes the compact global-index selection. The indexer and attention still compute the selection and run the Ulysses exchange in modeling. `tilelang` raises on an attention mask and falls back to `eager` with a warning for nonzero dropout, as on `main`. The non-QSA eager fallback in `eager_attention_forward` is gone because the vision tower binds its own `attention` op.	Same kernels and numerics. Qwen4-Exp RoPE now goes through `rope/partial`, so the GPU default `liger_kernel` applies where `main` used the HF eager function.
Causal Conv1D	Public default is `activation="silu"`, matching the model-path normal operation. The previous default was `None`.	Default-only; an explicit activation still wins.
Ascend implementation names	`main`'s `npu` rows are renamed after what they call: `torch_npu` (RMSNorm, RoPE, gated RMSNorm) and `triton` (causal Conv1D, chunk gated delta rule). `npu_ascendc` becomes `fla_npu`.	Naming only. Old values parse as deprecated aliases.
DeepSeek-V4 on Ascend	`main`'s NPU patch_gen calls the CANN Lightning Indexer, sparse FlashMLA and mHC kernels inside modeling code. Here they are `cann` rows of `dsa_indexer`, `dsa_attention` and `mhc` with the same structured contract as the GPU rows. The attention row converts global top-k indices to the segment-local indices CANN TND expects. `mhc/head/cann` is the eager math, as on `main`, since CANN has no head kernel. `main`'s unreferenced `npu_sparse_flash_mla_with_indexer_loss.py` is not ported.	Same kernels and arguments as `main`. `attention_mask` is still ignored, and calls without compressed rows still fall back to eager. The adapters no longer pre-check dtype or shape limits (for example the mHC bf16 check) and leave them to the kernel.
MoE implementation names	Registered names use the same `fused_triton`, `fused_quack`, `fused_npu`, and `fused_mlu` values exposed by configuration.	Naming only; fused implementations are unchanged.
Attention adapters	VeOmni names drop `_with_sp`: `veomni_flash_attention_*`, `veomni_flex_attention`, `veomni_magi_attention`.	Naming only.
SDPA packed metadata	`sdpa` is rewritten to `veomni_sdpa`. Packed/varlen metadata is dropped when it describes at most one segment per row or a 3-D/4-D mask isolates the segments. `packed_causal_mask` (and `sliding_window_mask` with `cu_seqlens`) builds a dense block-diagonal mask for SDPA. EFFICIENT/MATH backends are pinned only for masked calls.	Several packed samples in one row without an isolating mask now raise. `main` ignored the metadata and attended across samples. Masked forward matches HF `sdpa` bitwise. Backward is not bitwise where HF's default dispatch picks another backend (cuDNN on H20, up to 3.9e-3 on tiny bf16 models).
`eager` in non-HF families	Wan, Flux, Qwen Image, LTX, and MiniMax resolve `eager` to `veomni_sdpa`, and use `veomni_sdpa` as the masked fallback.	Same attention math through SDPA; not bitwise equal to `main`'s eager path.

Validation

The ops suite covers registry contracts, public signatures, forward and backward parity, hardware requirements, and optional dependency handling. The models suite covers construction, instance-local selection, family parity, and model-facing operator integration.

Trainer composition, ModelArguments path fallback, and SP ReduceLoss live with their owners rather than tests/models.

pytest tests/ops tests/models tests/arguments \
  tests/trainer/test_trainer_model_runtime.py \
  tests/trainer/test_channel_loss_callback.py \
  tests/distributed/test_reduce_loss.py \
  tests/lora/test_qwen3_5_moe_lora.py \
  tests/lora/test_dense_mlp_lora.py -q
make quality
patchgen --check

Latest local GPU result on 8× H20 for pytest tests/ops tests/models tests/lora tests/arguments, before the four fp32 loader cases were added to the oracle:

1862 passed, 73 skipped

make check-patchgen and the pre-commit hooks pass.

For the 53d5383 merge of #1197 / #970 / #1293 / #1300, the local 8× H20 results are as follows. The NPU paths of #970 and the Qwen4-Exp NPU generated file wait for CI.

CPU: pytest tests/ops tests/arguments tests/models tests/special_sanity tests/tools, plus the SeedOmni HF-layout and FLOPs tests, gives 1723 passed, 454 skipped
GPU: tests/ops/qsa_attention and tests/ops/gated_delta_rule give 48 passed, with NPU/MLU-only skips
GPU: tests/parallel/ulysses/test_qwen4_exp_ulysses.py on 4 GPUs gives 54 passed, including SP=4
GPU: test_qwen4_exp_training_smoke (SP=2, EP=2, PLE=2, qsa_attention_implementation=tilelang) passes

51d3898 merges #1279, the SeedOmni offline-cache workflow, which changes no op code. Only import paths and hf_layout.md anchors needed resolving.

CPU: the suites above plus tests/seed_omni and tests/checkpoints/test_{checkpoint_callback,dcp_checkpointer}.py give 2260 passed, 456 skipped, 4 failed
The 4 failures are test_dcp_checkpointer.py cases that call torch.cpu.empty_cache. They fail the same way on main with GPUs hidden

b60b81176 merges #1307 / #1309.

CPU: pytest tests/ops/gated_delta_rule/test_gated_delta_rule.py tests/arguments/test_ops_implementation_aliases.py, with the NPU and FLA cases deselected, gives 31 passed, 3 skipped. The skips are the new NPU sigmoid and CPU-cu_seqlens cases
make commit passed

e94f4950e sizes the NPU causal_conv1d parity case to the kernel tile (D=256). The forward without initial_state tiles the channel axis at 256. That case skips locally because this host has no NPU.

4b21b4c6d merges #1311.

make commit passed
The resolved SP/CP tests compile and pass ruff. GPU parity was not re-run

4140f586c merges #1264 / #1265.

make commit passed
The new short-segment case skips locally because this host has no NPU

Usage

Models construct an operation handle once and call it directly:

from veomni.ops import VeomniOp
from veomni.ops.config import resolve_op_impl


self.veomni_rms_norm = VeomniOp(
    "rms_norm",
    "standard",
    resolve_op_impl("rms_norm_implementation"),
)

hidden_states = self.veomni_rms_norm(
    hidden_states,
    self.weight,
    eps=self.variance_epsilon,
)

The exact registered and currently available implementations can be inspected through the registry:

from veomni.ops import OP_REGISTRY


OP_REGISTRY.list_registered("rms_norm", "standard")
OP_REGISTRY.list_available("rms_norm", "standard")
OP_REGISTRY.list_entries("rms_norm", "standard")

coderabbitai · 2026-08-31T04:38:31Z

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📒 Files selected for processing: 747

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configs/dit/minimax_h3_fl2va_offline.yaml
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veomni/ops/kernels/rope/deepseek_v4/eager.py
veomni/ops/kernels/rope/deepseek_v4/triton.py
veomni/ops/kernels/rope/full/__init__.py
veomni/ops/kernels/rope/full/eager.py
veomni/ops/kernels/rope/full/liger_kernel.py
veomni/ops/kernels/rope/full/torch_npu.py
veomni/ops/kernels/rope/interleave/__init__.py
veomni/ops/kernels/rope/interleave/eager.py
veomni/ops/kernels/rope/mrope/__init__.py
veomni/ops/kernels/rope/mrope/eager.py
veomni/ops/kernels/rope/partial/__init__.py
veomni/ops/kernels/rope/partial/eager.py
veomni/ops/kernels/rope/partial/liger_kernel.py
veomni/ops/kernels/rope/partial/torch_npu.py
veomni/ops/kernels/rope/wan/__init__.py
veomni/ops/kernels/rope/wan/eager.py
veomni/ops/kernels/rope/wan/torch_npu.py
veomni/ops/kernels/rope/wan/triton.py
veomni/ops/kernels/rotary/__init__.py
veomni/ops/kernels/rotary/npu.py
veomni/ops/kernels/rotary/triton_wan.py
veomni/ops/kernels/swiglu/__init__.py
veomni/ops/kernels/swiglu_mlp/__init__.py
veomni/ops/kernels/swiglu_mlp/geglu/__init__.py
veomni/ops/kernels/swiglu_mlp/geglu/eager.py
veomni/ops/kernels/swiglu_mlp/geglu/liger_kernel.py
veomni/ops/kernels/swiglu_mlp/standard/__init__.py
veomni/ops/kernels/swiglu_mlp/standard/eager.py
veomni/ops/kernels/swiglu_mlp/standard/liger_kernel.py
veomni/ops/liger/__init__.py
veomni/ops/mask.py
veomni/ops/platform/__init__.py
veomni/ops/platform/gpu.py
veomni/ops/platform/npu/hccl_premul_sum.py
veomni/ops/platform/requirement.py
veomni/ops/qat/__init__.py
veomni/ops/qat/_hardware.py
veomni/ops/qat/fp4_blockwise.py
veomni/ops/qat/fp8_blockwise.py
veomni/ops/qat/quant.py
veomni/ops/qat/scale.py
veomni/ops/registry.py
veomni/ops/triton_cache.py
veomni/trainer/base.py
veomni/trainer/callbacks/channel_loss_callback.py
veomni/trainer/callbacks/checkpoint_callback.py
veomni/trainer/dit_trainer.py
veomni/trainer/omni/omni_trainer.py
veomni/trainer/text_dpo_trainer.py
veomni/utils/device.py
veomni/utils/dit_utils.py
veomni/utils/import_utils.py
veomni/utils/save_safetensor_utils.py
veomni/utils/seqlen_pos_transform_utils.py

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Coach257 · 2026-08-31T06:24:07Z

#1073

…omniOp Authors register raw forward/backward or an opaque wrapper. The registry generates the autograd Function, keys rows by (op, variant, impl, device), and hands modeling a local VeomniOp. Delete the old kernel_registry, dispatch, and config singleton so the public API has one registration path.

…l loss Move the common tensor ops onto OP_REGISTRY with eager and vendor rows. Keep CE and load-balancing at token level; shifting, SP reduction, and log-prob policy stay out of the kernel rows. Include LayerNorm so async Ulysses does not depend on Apex.

Add the remaining compute families as registry rows, including LoRA expert variants and device-specific implementations. Compound or opaque ops keep raw nested calls where a clean forward/backward split exists.

Install stock and veomni_* attention into the Transformers registries. Keep mask builders as a separate shape/native API. Async Ulysses QKV/O uses standard and dit variants that call nested raw pairs.

…andles Model construction, checkpoint convert/load, and loss helpers resolve ops from config and store VeomniOp on the instance. There is no process-wide bind. Shared tests cover registry build, config scope, and handle isolation.

Point every supported text, VL, and Omni family at instance-local VeomniOp handles. Keep patchgen configs and generated modeling in the same commit so the registered classes match the new call sites.

Consume Wan, Flux, Qwen Image, LTX, MiniMax, and MoVQGAN through the same VeomniOp handles as the transformer families, including DiT async Ulysses and family-specific attention wiring.

Update trainer, sequence-parallel, LoRA, data, and YAML defaults to the new op names and instance-local handles. Drop leftover slot/facade rewrites so callers cannot select interned names that no longer exist.

Describe OpEntry, VeomniOp, and selection in current docs and skills. Point patchgen, device-api, and unit-test workflows at the canonical ops and models packages.

… and NPU checks Co-authored-by: Cursor <cursoragent@cursor.com>

… checks Co-authored-by: Cursor <cursoragent@cursor.com>

Co-authored-by: Cursor <cursoragent@cursor.com>

Pin the SwiGLU routing scale to the activation dtype so batch-invariant linear does not mix fp32 router scores with bf16 expert weights. Align the Wan padded Ulysses reference to the same mask, skip Qwen-Image isolation on NPU CPU tensors, and give DeepSeek-V3 e2e the same bf16 mixed-precision extra_args as V4. Co-authored-by: Cursor <cursoragent@cursor.com>

… on compute dtype Drop the GPU eager-MoE override so DeepSeek-V3 e2e stays on fused_triton with the original EP=2 matrix. Cast fp32 router scores onto the activation dtype at the experts call site and in the Triton wrapper so group-gemm does not see a dtype split. Co-authored-by: Cursor <cursoragent@cursor.com>

Co-authored-by: Cursor <cursoragent@cursor.com>

…s, and NPU detection Co-authored-by: Cursor <cursoragent@cursor.com>

…h VeomniOp Co-authored-by: Cursor <cursoragent@cursor.com>

- Implement shared-prefix training for Qwen3.5 and Qwen3.5 MoE on GPU and NPU - Adapt GatedDeltaNet and Attention layers to VeomniOp interface (ByteDance-Seed#1142) - Fork recurrent state for GatedDeltaNet at prefix boundary - Gather key/value states for Attention across prefix and suffix - Add shared prefix plan layout and compaction utilities - Add comprehensive unit tests and documentation

…tern Follow-up to the origin/main merge (ByteDance-Seed#1142 OpSlot -> VeomniOp refactor): - KimiRMSNorm / SituAndMul: __init__-bound instance-local VeomniOp handles (rms_norm/standard, situ_and_mul/kimi_k3) replacing the OpSlot guards - PatchedKimiK3Experts: branchless dispatch through an instance-local moe_experts VeomniOp (kimi_k3 variant for SituGLU, standard otherwise); the eager expert loop is now a registered row, not an in-rule fallback - CE loss: ForCausalLMLoss bound to a cross_entropy_loss/standard VeomniOp via functools.partial on both KimiLinearForCausalLM and KimiK3ForConditionalGeneration (variant renamed causal -> standard) - chunk_kda: name hijack now dispatches through a lazily-resolved chunk_kda/kimi_k3 VeomniOp (first-call resolution follows the ops config installed at model-build time) - NPU config re-registers the new __init__ overrides; regen both targets

…le via VeomniOp Merge #1314 (including #1142 VeomniOp refactor) into omniv2 alongside the per-module SP/CP/CP*SP support, and migrate SeedOmni modules onto explicit VeomniOp selection from self.config.ops_implementation: - BagelQwen2MoTAccelerated, BagelSiglipNavit, TextEncoderAccelerated, JanusVqvaeAccelerated, Qwen3MoeLlm: replace module-level OpSlot / global LOSS_MAPPING / direct kernel dispatch with instance-local VeomniOp handles constructed directly from config.ops_implementation.get(...). - JanusSiglipConfig: declare sub_configs = {"vision_config": JanusVisionConfig} so _attn_implementation propagates to the nested vision config. - OmniModel._load_modules, ModuleRuntime._init_eager_inference: drop global set_ops_config / bind_ops_to_modeling calls.

…MiniMax M3 VL support MiniMax M3 VL (MiniMaxAI/MiniMax-M3) support rebuilt on main after the OpSlot -> VeomniOp refactor (ByteDance-Seed#1142), the moe_experts reorganisation, and the test-tree reorganisation. - Modeling: patchgen GPU/NPU configs construct instance-local VeomniOps: rms_norm/offset (fp32 1 + weight), cross_entropy_loss via ForCausalLMLoss, moe_experts/swiglu_oai, minimax_sparse_attention indexer/attention, and attention/standard for the vision tower. Packed-only language attention, Ulysses with per-KV-group index-query exchange, frozen indexer, vision attention guard for varlen and veomni_* backends, router aux loss disabled. - Ops: minimax_sparse_attention eager rows (npu_fusion_attention on Ascend); moe_experts/swiglu_oai rows (eager, fused_triton, fused_npu) reusing the standard merged-fc1 Triton/NPU/EP paths through an optional swiglu_alpha; SwiGLU-OAI helpers in moe_experts/shared/swiglu.py; Ulysses gather_seq_scatter_kv_heads. - Data/trainer: MiniMax processor, chat template and data transform; shared VLM media loading; vision_tower lookup and vit_lr grouping. - Checkpoint: runtime converter for the public checkpoint layout. - Tests, configs and docs for the above.

…nce-Seed#1142) Co-authored-by: Cursor <cursoragent@cursor.com>

github-actions Bot added the wip label Aug 31, 2026

Zx55 changed the title ~~WIP: replace OpSlot dispatch with KERNEL_REGISTRY~~ WIP: refactor OpSlot dispatch Aug 31, 2026

Coach257 reviewed Sep 3, 2026

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Comment thread tests/kernels/attention_cases.py Resolved

Coach257 reviewed Sep 3, 2026

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Comment thread configs/multimodal/qwen3_5_moe/qwen3_5_moe_vl.yaml Resolved

Coach257 reviewed Sep 3, 2026

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Comment thread tests/ops/mhc/test_mhc.py Resolved

Coach257 reviewed Sep 3, 2026

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Comment thread veomni/ops/kernels/async_ulysses/o_proj/standard/eager.py Resolved

Coach257 reviewed Sep 7, 2026

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Comment thread veomni/models_kernel/transformers/qwen3_5_moe/qwen3_5_moe_gpu_patch_gen_config.py Resolved

Coach257 mentioned this pull request Sep 10, 2026

[ops] feat: external ops-backend plugin loader via entry points #1121

Open

Zx55 changed the title ~~WIP: refactor OpSlot dispatch~~ [ops, model] refactor: replace OpSlot with OP_REGISTRY and VeomniOp Sep 18, 2026

Zx55 changed the title ~~[ops, model] refactor: replace OpSlot with OP_REGISTRY and VeomniOp~~ [ops, model] refactor: replace OpSlot with VeomniOp Sep 18, 2026

Zx55 changed the title ~~[ops, model] refactor: replace OpSlot with VeomniOp~~ [BREAKING][ops, model] refactor: replace OpSlot with VeomniOp Sep 20, 2026

Zx55 added 9 commits September 20, 2026 11:49

[ops] feat: register MoE, GDN, DSA, mHC, and QAT

9273b55

Add the remaining compute families as registry rows, including LoRA expert variants and device-specific implementations. Compound or opaque ops keep raw nested calls where a clean forward/backward split exists.

[ops, parallel] feat: register attention, masks, and async Ulysses

6aee514

Install stock and veomni_* attention into the Transformers registries. Keep mask builders as a separate shape/native API. Async Ulysses QKV/O uses standard and dit variants that call nested raw pairs.

[model] refactor: migrate transformer families onto the op registry

13ac945

Point every supported text, VL, and Omni family at instance-local VeomniOp handles. Keep patchgen configs and generated modeling in the same commit so the registered classes match the new call sites.

[model] refactor: migrate diffusion families onto the op registry

f431b63

Consume Wan, Flux, Qwen Image, LTX, MiniMax, and MoVQGAN through the same VeomniOp handles as the transformer families, including DiT async Ulysses and family-specific attention wiring.

[trainer, dist, lora, config] refactor: point callers at the op registry

5e14133

Update trainer, sequence-parallel, LoRA, data, and YAML defaults to the new op names and instance-local handles. Drop leftover slot/facade rewrites so callers cannot select interned names that no longer exist.

[docs, agent, ci] chore: document the op registry and update CI

c29b58f

Describe OpEntry, VeomniOp, and selection in current docs and skills. Point patchgen, device-api, and unit-test workflows at the canonical ops and models packages.

Zx55 force-pushed the czr/kernel-registry-refactor branch from 520a68c to c29b58f Compare September 20, 2026 03:51

Zx55 marked this pull request as ready for review September 20, 2026 04:11

Zx55 and others added 3 commits September 20, 2026 12:47

[model, test, docs] fix: repair registry CI import, device-api, docs,…

05d69a3

… and NPU checks Co-authored-by: Cursor <cursoragent@cursor.com>

[test] fix: repair remaining device-api, e2e dtype, and NPU isolation…

c5460f7

… checks Co-authored-by: Cursor <cursoragent@cursor.com>

[ops, test] fix: pin full RoPE saved tables to q.dtype

b47007f

Co-authored-by: Cursor <cursoragent@cursor.com>

NancyFyong mentioned this pull request Sep 20, 2026

[model, trainer] feat: pack MiniMax H3 offline training #1204

Merged

Zx55 and others added 2 commits September 20, 2026 22:40

Coach257 reviewed Oct 17, 2026

View reviewed changes

Zx55 and others added 7 commits October 18, 2026 01:12

[model] chore: merge github/main into kernel-registry-refactor

ddc0194

Co-authored-by: Cursor <cursoragent@cursor.com>

[test] fix: import Qwen-Image registries from the current model package

7f72048

Co-authored-by: Cursor <cursoragent@cursor.com>

fix: address PR ByteDance-Seed#1142 review feedback on RoPE, MoE, los…

293e618

…s, and NPU detection Co-authored-by: Cursor <cursoragent@cursor.com>

[model, test] fix: align Wan SP RoPE and Qwen-Image NPU mask test wit…

8e93906

…h VeomniOp Co-authored-by: Cursor <cursoragent@cursor.com>

[ops] refactor: resolve default implementations in the registry

f961098

[test] fix: preserve op metadata and Diffusers CPU normalization

e68ec21

[ops, test] fix: stabilize Liger RoPE checkpoint metadata

d36a89f

Coach257 approved these changes Oct 18, 2026

View reviewed changes

Coach257 merged commit 8305980 into ByteDance-Seed:main Oct 18, 2026
18 checks passed

Zx55 mentioned this pull request Oct 19, 2026

[ops] feat: select Flex/Magi by GPU generation #1321

Merged

Coach257 mentioned this pull request Oct 20, 2026

[ops] fix: honor sigmoid activation in npu gated rmsnorm #1223

Closed

Zx55 mentioned this pull request Oct 20, 2026

[ops, model] refactor: support packed varlen cu_seqlens splitting in attention wrapper #1327

Merged

5 tasks done

Coach257 mentioned this pull request Oct 21, 2026

[ops, model] refactor: separate chunk logprobs device kernels into veomni/ops #1338

Merged

5 tasks done

yeyeyeping mentioned this pull request Oct 21, 2026

[model, ops, data, trainer, ckpt, ci, config, docs, agent] feat: add MiniMax M3 VL support #1315

Open

4 tasks done

This was referenced Oct 23, 2026

[omni, ckpt, ops, misc] feat: adapt shared components to module-level runtimes #1065

Closed

[BREAKING][ops, omni, model] refactor: make op and kernel selection per-module #1073

Closed

sc1915 pushed a commit to sc1915/VeOmni that referenced this pull request Oct 23, 2026

[BREAKING][ops, model] refactor: replace OpSlot with VeomniOp (ByteDa…

00fc591

…nce-Seed#1142) Co-authored-by: Cursor <cursoragent@cursor.com>

xiaohong42 mentioned this pull request Oct 25, 2026

[ops] feat: run the DeepSeek-V4 TileLang kernels and FP8 QAT on AMD gfx942/gfx950 #1363

Open

5 tasks done

Zx55 mentioned this pull request Oct 26, 2026

[ops, model, lora] refactor: move MoE routing weight dtype casts into ops #1367

Merged

Coach257 mentioned this pull request Oct 26, 2026

[model, ci] fix: unify prepare_dense_attention_inputs across dense attention models #1368

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zhtmike mentioned this pull request Oct 27, 2026

[RFC][tracking] Upstream patch debt: audited ledger of temporary compatibility patches verl-project/verl-omni#445

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38 tasks

Zx55 mentioned this pull request Oct 28, 2026

[BREAKING][model, ops] refactor: use module-level ops config #1379

Merged

xiaohong42 mentioned this pull request Nov 1, 2026

[recipe, hardware] fix: drop the DeepSeek-V4 recipe's vLLM B-preshuffle check that refuses every vLLM on gfx94x xiaohong42/verl#4

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6 of 8 tasks

Zx55 mentioned this pull request Nov 3, 2026

[omni, model, ops, ckpt, config, docs] feat: support Bagel in SeedOmni #1402

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[BREAKING][ops, model] refactor: replace OpSlot with VeomniOp - #1142

[BREAKING][ops, model] refactor: replace OpSlot with VeomniOp#1142
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