v1.8.0

What's Changed

• Remove signal initalizations by @tmeissner in #464
• Upgrade on-chip-debugger by @stnolting in #463
• ⚠️ rework CPU debug spec ISA configuration; ✨ enhance trigger module by @stnolting in #465
• [sw] rename library functions by @stnolting in #467
• [rtl] OCD: update DTM and DM by @stnolting in #468
• Fix value of SYSINFO_SOC_IO_ONEWIRE in NEORV32_SYSINFO_SOC_enum by @tmeissner in #469
• [rtl] CPU: logic optimization by @stnolting in #470
• [sw/example/demo_spi_irq]: make read/write data pointer and busy flag… by @akaeba in #471
• [rtl] update TRNG by @stnolting in #472
• [rtl/test_setups] add on-chip debugger test setup by @stnolting in #473
• ⚠️ rework watchdog timer (WDT) by @stnolting in #474
• [rtl] VHDL cleanups by @stnolting in #476
• ⚠️ Rework CPU counters by @stnolting in #477
• [sw] cleanup and update software framework by @stnolting in #478

Full Changelog: v1.7.9...v1.8.0

v1.7.9

What's Changed

• [rtl] cleanup main package file by @stnolting in #447
• [sw] rework intrinsic libraries by @stnolting in #448
• ✨ Add CFU R4-type instructions by @stnolting in #449
• 🐛 [rtl] core trap fixes by @stnolting in #450
• [sw] Remove B ISA extension intrinsic library by @stnolting in #451
• ✨ [CFU] add support for custom R5-type instructions by @stnolting in #452
• [rtl] instruction prefetch buffer (IPB) improvements by @stnolting in #455
• 🧪 [OCD] optimize firmware (park-loop) by @stnolting in #456
• 🐛 [rtl] fix iCache block error bug by @stnolting in #457
• 🐛 [rtl] fix MEPC value for instruction access faults by @stnolting in #458
• [rtl] mtval CSR is now r/w by @stnolting in #460
• [rt] SoC: rework r/w access logic and reset by @stnolting in #461
• [rtl] CPU: optimizations and cleanup by @stnolting in #462

Full Changelog: v1.7.8...v1.7.9

v1.7.8

What's Changed

• 🐛 [.github] disable Windows/MSYS2 workflows for now by @stnolting in #424
• Fix Critical Warning in Quartus 20.1.0: avoid power up to high by @akaeba in #423
• litex_core_complex: Expose configuration constants as generics. by @enjoy-digital in #425
• Add HW reset to CPU counter CSRs by @stnolting in #426
• 🐛 [rtl] fix is_power_of_two VHDL function by @stnolting in #428
• 🐛 [sw/lib] fix UART "char_received" function by @stnolting in #431
• [rtl] Optimize UART RTS behavior by @stnolting in #433
• [rtl] Try to fix Quartus latch warnings by @stnolting in #434
• ✨ [sw] add assembly-only demo program by @stnolting in #436
• [sw] rename blink_led example -> demo_blink_led by @stnolting in #435
• ⚠️ rework SPI module by @stnolting in #438
• ⚠️ rework TWI module by @stnolting in #440
• [rtl] minor rtl edits by @stnolting in #441
• [rtl] rlt/code cleanups & optimizations by @stnolting in #442

New Contributors

• @enjoy-digital made their first contribution in #425

Full Changelog: v1.7.7...v1.7.8

v1.7.7

What's Changed

• ✨ Add 1-Wire Interface Controller by @stnolting in #402
• [sw] remove 'register' qualifier by @stnolting in #404
• [rtl] Cleanup hardware reset logic by @stnolting in #405
• [rtl] minor edits and cleanups by @stnolting in #406
• ⚠️ [rtl] cleanup CPU standard counters, remove CPU_CNT_WIDTH generic by @stnolting in #407
• [rtl] minor edits of FIFO module by @stnolting in #408
• [rtl] set 'mtval' CSR to zero if illegal instruction exception by @stnolting in #409
• [rtl] minor edits and cleanups by @stnolting in #410
• 🐛 [rtl] fix minor bug in mie CSR (FIRQs) by @stnolting in #411
• 🐛 [rtl] fix B ISA instruction decoding collisions by @stnolting in #413
• Fix typo. by @ahmedcharles in #416
• [rtl] XLEN cleanup by @stnolting in #417

Full Changelog: v1.7.6...v1.7.7

v1.7.6

What's Changed

• change base address of BUSKEEPER by @stnolting in #385
• [rtl] relocate TWI tri-state drivers by @stnolting in #386
• [rtl] optimize instruction fetch by @stnolting in #387
• [rtl/PWM] minor cleanup by @stnolting in #388
• 🔒 [TRNG] add read data security feature by @stnolting in #389
• 🚀 [sw] Update software framework to GCC 12.1.0 by @stnolting in #391
• [rtl] minor edits and cleanups by @stnolting in #396
• [sw} cleanup crt0 start-up code by @stnolting in https://github.com//pull/397
• [rtl] core cleanup / minor fixes by @stnolting in #398
• 🚀 [docs] add neorv32-verilog repository by @stnolting in #400

Full Changelog: v1.7.5...v1.7.6

v1.7.5

What's Changed

• 🐛 [rtl] cycle & instret bug fix, wishbone.we bug fix; minor rtl updates by @stnolting in #367
• 🐛 [rtl] fix PMP config by @stnolting in #368
• [rtl] minor edits and updates by @stnolting in #369
• [ug] add new section "LiteX Support" by @stnolting in #370
• 🔒 Specifiy Physical Memory Attributes by @stnolting in #372
• [rtl] add CUSTOM_ID generic by @stnolting in #374
• [sw] add ISR based SPI data flow example by @akaeba in #373
• ⚠️ [linker script] simplify memory configuration by @stnolting in #375
• ⚠️ [rtl] rework SLINK module by @stnolting in #377
• [sw example] demo_spi_irq can handle FIFO by @akaeba in #382
• ✨ [rtl] add optional SPI data FIFO by @stnolting in #381
• [rtl] minor cleanups and optimizations by @stnolting in #383
• [rtl] minor cleanup by @stnolting in #384

Full Changelog: v1.7.4...v1.7.5

v1.7.4

What's Changed

• 🐛 fix CPU stall on illegal LD/ST instruction by @stnolting in #356
• 🧪 [rtl/system_integration] add LiteX core complex wrapper by @stnolting in #353
• [rtl] minor cleanups and typo fixes by @stnolting in #357
• [rtl] add "cached access" infrastructure by @stnolting in #359
• [image_generator, makefile] Update "raw" executable formats by @stnolting in #360
• 🧪 [XIP] add experimental burst mode; fix endianness by @stnolting in #361
• 🐛 [bootloader] fix flash byte-order by @stnolting in #362
• Fix PMP locking by @stnolting in #363
• [sw] update bootloader by @stnolting in #364
• 🐛 [PMP] rework and fixes by @stnolting in #365
• [rtl] reset all "core" CSRs to zero by @stnolting in #366

Full Changelog: v1.7.3...v1.7.4

v1.7.3

What's Changed

• ✨ Add watchdog pause flag by @stnolting in #331
• [rtl] add hardware reset to IO/peripheral devices by @stnolting in #334
• 🐛 fix SPI & XIP clock phase offset by @stnolting in #336
• [rtl] split executable images into package and body by @akaeba in #338
• [rtl] rework TWI module by @stnolting in #340
• [rtl] add Wishbone output "gating" by @stnolting in #344
• [rtl] rework reset system by @stnolting in #345
• ⚠️ [rtl] rework SLINK module by @stnolting in #349
• [rtl] minor clean-ups/optimizations by @stnolting in #351
• [rtl] add "async TX" Wishbone option by @stnolting in #352

New Contributors

• @akaeba made their first contribution in #338

Full Changelog: v1.7.2...v1.7.3

🎉 Two years NEORV32! 😄

v1.7.2

What's Changed

• ⚠️ remove CPU's A ISA extension (atomic memory access) by @stnolting in #308
• Add further mxisa CSR flags by @stnolting in #309
• 🐛 fix bug in CPU counter overflow logic by @stnolting in #310
• update to new neoTRNG v2 by @stnolting in #311
• Cleanup bitmanip co-processor by @stnolting in #312
• 🐛 fix buskeeper timeout error by @stnolting in #315
• [TRNG] add optional/configurable data FIFO by @stnolting in #316
• 🐛 fix XIP sub-word accesses by @stnolting in #320
• crt0.S: Do not clear XIP control registers except in bootloader mode by @jpf91 in #318
• [linker script, crt0] align all sections to 32-bit boundaries by @stnolting in #323
• Constructors by @GideonZ in #324
• 🐛 Fix sync. vs. async. exception collision by @stnolting in #327
• rework bootloader's SPI flash access by @stnolting in #321
• Bugfix - eliminates potential shift of data by 4 bytes. by @GideonZ in #313
• 🐛 fix debugger single-instruction stepping mode by @stnolting in #329

New Contributors

• @jpf91 made their first contribution in #318
• @GideonZ made their first contribution in #324

Full Changelog: v1.7.1...v1.7.2

v1.7.1

What's Changed

• Rework register file's "zero" register by @stnolting in #298
• 🧹 [rtl] CPU frontend cleanup by @stnolting in #299
• [rtl] make CPU front-end synchronous by @stnolting in #300
• [rtl] optimize CPU barrel shifter timing by @stnolting in #301
• VHDL code clean-ups by @stnolting in #303
• Processor check edits by @stnolting in #304
• [rtl] optimize CPU mul/div unit by @stnolting in #305
• ✨ [rtl] add simple branch prediction by @stnolting in #306

ℹ️ See CHANGELOG.md for more details.

Full Changelog: v1.7.0...v1.7.1