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🐛 [PMP] rework and fixes #365

Merged
merged 14 commits into from
Jul 14, 2022
Merged

🐛 [PMP] rework and fixes #365

merged 14 commits into from
Jul 14, 2022

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@stnolting stnolting commented Jul 13, 2022 •
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This PR reworks/fixes the processor's physical memory protection (PMP):

  • ✔️ the PMP mechanism is completely reworked (because of a misunderstanding on my side): "In general, the PMP can grant permissions to U mode, which by default have none, and can revoke permissions from M-mode, which by default has full permissions." - RISC-V spec.; the PMP now complies to these specs.
  • ✨ added mstatus.PMP flag: when set M-mode software uses the privilege from mstatus.MPP for load/store accesses (to emulate unprivileged accesses)
  • ✨ removed pmp_num_regions_critical_c configuration constant; load/store memory access latency is nof affected by the PMP - regardless of the number of implemented PMP regions
  • ⚠️ the NEOR32 PMP still only supports TOR (top of region; bound and base concept) and OFF modes; NAPOT and NA4 are not supported (yet)

@stnolting stnolting added risc-v compliance Modification to comply with official RISC-V specs. HW Hardware-related labels Jul 13, 2022
@stnolting stnolting self-assigned this Jul 13, 2022
@stnolting stnolting marked this pull request as ready for review July 13, 2022 19:13
@stnolting stnolting added the bug Something isn't working as expected label Jul 13, 2022
@stnolting stnolting changed the title [PMP] rework and fixes 🐛 [PMP] rework and fixes Jul 13, 2022
@stnolting stnolting merged commit 7170967 into main Jul 14, 2022
@stnolting stnolting deleted the rework_fix_pmp branch July 14, 2022 07:23
@stnolting stnolting mentioned this pull request Jul 15, 2022
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bug Something isn't working as expected HW Hardware-related risc-v compliance Modification to comply with official RISC-V specs.
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