[rtl] add "async TX" Wishbone option

[stnolting]

This PR adds another configuration option for the external memory interface (Wishbone). By default, all incoming and outgoing Wishbone signals are registered to allow easy timing closure even when using complex (combinatorial) Wishbone interconnection networks.

The processor already provides the MEM_EXT_ASYNC_RX option to omit the register stage for incoming signals (seen from the processor). The new MEM_EXT_ASYNC_TX option now allows to also omit the register stage for outgoing signals.

Each enabled option will reduce the external memory interface latency by 1 cycle. If both options are enabled an external memory can be accessed with the same latency as any processor-internal memory.