v1.6.9

What's Changed

• [rtl/core] rework CPU data path by @stnolting in #279
• 🐛 [rtl/core] fix bug in mip CSR clear/acknowledge by @stnolting in #280
• ⚠️ Rework physical memory protection (PMP) [NAPOT -> TOR] by @stnolting in #281
• Update neorv32_gptmr.c by @prdwivedi in #282
• 🐛 [PMP] fix pmpaddr CSR layout by @stnolting in #283
• [rtl] CPU code clean-up; add RISC-V mstatus.TW CSR bit by @stnolting in #285

ℹ️ See CHANGELOG.md for more details.

New Contributors

• @prdwivedi made their first contribution in #282

Full Changelog: v1.6.8...v1.6.9

v1.6.8

What's Changed

• ✨[Zxcfu ISA ext.] add option to implement custom RISC-V instructions by @stnolting in #264
• 🐛 [sw] fixed bug in bootloader's (M)TIME handling by @stnolting in #267
• 🧪 Using LTO (link-time-optimization) for bootloader + console improvements by @stnolting in #268
• [docs/datasheet] rework & update NEORV32 runtime environment (RTE) section by @stnolting in #272
• [rtl] add err_o signal to IMEM modules by @stnolting in #273
• ✨ [rtl] on-chip debugger: add RISC-V trigger module for hardware breakpoints by @stnolting in #274
• [sw] add support for newlib's system calls by @stnolting in #275
• ⚠️ replace SYSINFO.CPU memory-mapped register by custom "mxisa" CSR by @stnolting in #276
• [OCD] stop CPU counters during debugging by @stnolting in #277
• Add newlib example program and documentation by @stnolting in #278

Full Changelog: v1.6.7...v1.6.8

v1.6.7

What's Changed

• [setups] move to repo neorv32-setups by @umarcor in #254
• [rtl/core] rework CPU issue engine (area optimization) by @stnolting in #256
• [DOC] User Guide - 1.3. Installation by @befedo in #258
• [B ISA extension] add single-bit instructions (Zbs) support by @stnolting in #259
• [B ISA extension] add carry-less multiply instructions (Zbc) support by @stnolting in #260
• [CFS] add demo program by @stnolting in #261
• [rtl/core] add 4 additional CPU CP slots; fix bugs in CP arbitration logic by @stnolting in #262
• [sw] rework intrinsics (e.g. for custom instructions) by @stnolting in #263

New Contributors

• @befedo made their first contribution in #258

Full Changelog: v1.6.6...v1.6.7
Project Changelog: CHANGELOG.md

v1.6.6

What's Changed

• Fix compile error with questa, for issue #242 by @tmeissner in #243
• ⚠️ Make PWM and XIRQ IOs fixed-sized by @stnolting in #241
• ✨ Add Execute In Place (XIP) Module by @stnolting in #244
• [rtl/core/mem] Rename legacy-style memory files by @stnolting in #246
• [.github/riscv-arch-test] Fix / rework by @stnolting in #248
• [BUSKEEPER] Add NULL address check option by @stnolting in #247
• ⚠️ [XIP] reworked execute in place module by @stnolting in #249
• [SPI & XIP] add high-speed SPI mode option by @stnolting in #251
• setups/osflow/synthesis: recent versions of yosys need command 'read_verilog' by @umarcor in #252
• 🐛 [BUSKEEPER] fix bug in error flag logic by @stnolting in #253
• [GPIO] raise bus exception if writing to INPUT registers by @stnolting in #255

Full Changelog: v1.6.5...v1.6.6

v1.6.5

What's Changed

• Fix neorv32_gpio_port_get() by @hipolitoguzman in #223
• [docs/userguide] split user guide into several files by @stnolting in #222
• TRNG and Vivado block designs by @stnolting in #229
• ⚠️ Remove legacy SW (compatibility) wrappers by @stnolting in #228
• 🐛 Fix Wishbone timeout bug by @stnolting in #230
• Add SYSINFO flag to check if processor is being simulated by @stnolting in #231
• Add a System View Description (SVD) file by @stnolting in #225
• ⚠️ Rework FIRQ System (re-rework): use MIP to clear/ack IRQs by @stnolting in #236
• [sw/example] add SLINK demo program by @stnolting in #235
• 📚 [SW makefile] add variables to help target by @stnolting in #237
• MULDIV optimization by @stnolting in #238
• Watchdog [WDT]: add option to enable/disable WDT during debugging by @stnolting in #239
• [setups/osflow] update README by @stnolting in #221
• Faster mul/div operations by @stnolting in #240

New Contributors

• @hipolitoguzman made their first contribution in #223

Full Changelog: v1.6.4...v1.6.5

nightly

🚀 Up-to-date automatic builds of the documentation and project source packaging (see the assets).

• NEORV32-nightly.pdf - Data Sheet, also available online
• NEORV32_UserGuide-nightly.pdf - User Guide, also available online

v1.6.4

Bug Fixes

• fixed bug in WISHBONE interface: pipelined Wishbone mode did not clear STB after first transfer cycle
• on-chip debugger: reworked JTAG signal input/output synchronization logic (#216) - JTAG signals were not correctly sampled at the right rising/falling clock edges

Updates and New Features

• reworked TRNG (#212)
• ⚠️ removed WI_CTRL_CKSTEN flag (enable clock stretching) from control registers, clock-stretching is now always enabled
• major control unit and AKU logic optimizations; 🔒 closed further illegal instruction encoding holes (system environment instructions, ALU and ALU-immediate instructions, FENCE instructions) (#204)
• ⚠️ reworked IRQ trigger logic of SPI, TWI, UART0, UART1, NELOED and SLINK; FIRQs now only trigger once when the programmed interrupt condition is met instead of triggering all the time (#202)
• added new peripheral module - General Purpose 32-bit Timer GPTMR (#195)

What's Changed

• Add a Gitter chat badge to README.md by @gitter-badger in #196
• Add general purpose timer GPTMR by @stnolting in #195
• Add cyclone2 legacy mem-files by @stnolting in #198
• [ci] use option 'pacboy' to simplify workflow 'Windows' by @umarcor in #201
• Rework peripheral's FIRQ triggering by @stnolting in #202
• Added neorv32-examples by @emb4fun in #205
• CPU logic optimization by @stnolting in #204
• [TWI] remove clock-stretching enable flag by @stnolting in #209
• setups/osflow/Makefile: support overriding variables by @umarcor in #214
• Rework TRNG module by @stnolting in #212
• Added a example serial terminal program for Linux by @qwqw330 in #215
• [On-Chip Debugger] Fix JTAG timing by @stnolting in #216
• Add iCEBreaker Board to the osflow by @lab-mathias-claussen in #217
• Adding the possibility of indicate external sources throw a enviromen… by @zipotron in #213

New Contributors

• @gitter-badger made their first contribution in #196
• @emb4fun made their first contribution in #205
• @qwqw330 made their first contribution in #215
• @lab-mathias-claussen made their first contribution in #217

Full Changelog: v1.6.3...v1.6.4

v1.6.3

Bug Fixes

• fixed bug in *_reduce_f VHDL functions (#186)
• fixed imprecise illegal instructions exception (ALU-class operations); mepc and mtval did not present the correct exception-causing data

Updates and New Features

• ⚠️ removed CPU_EXTENSION_RISCV_Zbb, added CPU_EXTENSION_RISCV_B generic (#190)
  • all currently supported bit-manipulation sub-extensions are enabled/disabled by the CPU_EXTENSION_RISCV_B generic
  • added support of Zba (address computation instructions) bit-manipulation sub-extension
• added generics to explicitly enable Zicntr and Zihpm extensions (#192)
  • CPU_EXTENSION_RISCV_Zicntr, true by default, implements basic CPU counter CSRs ([m]time, [m]cycle[h], [m]instret[h])
  • CPU_EXTENSION_RISCV_Zihpm, false by default, implements hardware performance monitor CSRs
• added memory-mapped register to BUSKEEPER to identify precise cause of bus access exceptions (#191)
• bootloader now uses physical memory configuration (from SYSINFO) module to setup stack pointer
• added option to configure clock polarity and clock phase of SPI module (#185)
• minor logic optimizations (reducing area footprint and shortening critical path) and code clean-ups

What's Changed

• [SPI] Add CPOL (clock polarity) configuration option by @stnolting in #185
• fix: reduce_f won't work with single bit operands by @gottschalkm in #186
• [setups/ULX3S] increase memory sizes to "default" by @stnolting in #188
• [B ISA Extension] Rework and addition of Zba subset by @stnolting in #190
• [BUSKEEPER] add memory-mapped status register by @stnolting in #191
• RISC-V "Zicntr" and "Zihpm" extensions by @stnolting in #192

Closed Issues

• #140 Usage of Logic Elements almost double when synthesizing for Max 10
• #145 Radiant setup fails to build with Radiant 2.2.1.239.2
• #169 SDRAM controller for the ULX3S
• #181 neorv32/docs/userguide/content.adoc en dash / em dash

New Contributors

• @gottschalkm made their first contribution in #186

Full Changelog: v1.6.2...v1.6.3

v1.6.2

This list shows the main core changes since the last release. See the project's changelog for more information.

🐛 Bug Fixes

• fixed signal and generic propagation in rtl/system_integration and setups/radiant/UPduino_v3

💡 Updates and New Features

• ⚠️ changes handling of software makefile's MARCH and MABI variables (see #184): omitting -march and -mabi flags for these variables
• ⚠️ reworked fast interrupt request (FIRQ) CPU system: FIRQs are now high-level-triggered and have to stay asserted until explicitly acknowledged (see #176)
• ⚠️ removed mstatus.TW (timeout wait) CSR bit: wfi instruction is now always allowed to execute in less-privileged modes
• ⚠️ removed sleep_i signal of custom functions subsystem (CFS)
• 🔒 CPU now ensures that all illegal instructions do not commit any potential architecture state changes
• on-chip debugger: wfi now executes as nop when in debug-mode (also during single-stepping)
• NEOLED: added new control register bit to configure interrupt condition
• SLINK: added fine-grained per-link interrupt configuration (see #182)
• UART0, UART1: added optional and configurable RX and TX FIFOs, added fine-grained IRQ configuration (see #183)
• CPU logic, timing and area optimizations

✔️ Pull Requests and Issues

Merged pull requests:

• #170 🐛 [rtl/system_integration] fix uart1 rx/tx signals
• #173 Add argument to makefile to simplify Continuous Integration flow
• #174 [setups/vivado] Mention the XHub Stores menu item for installing board support
• #175 [setups/vivado] Fix fileset paths
• #176 [rtl/core] make FIRQs level-triggered
• #177 [docs/datasheet] Fix neoled register bits documentation
• #178 [rtl/system_integration] add NEOLED FIFO depth generic to AXI4 wrapper
• #180 [docs/datasheet] fix neoled register table formatting
• #182 [SLINK] add fine-grained IRQ configuration
• #183 [UARTs] add RX & TX FIFOs
• #184 ⚠️ [makefile] modify handling of MARCH and MABI variables

Closed issues:

• #171 Make Check Fails (riscv32-unknown-elf-gcc is not found)
• #181 neorv32/docs/userguide/content.adoc en dash / em dash

v1.6.1

This list shows the main core changes since the last release. See the project's changelog for more information.

🐛 Bug Fixes

• fixed bug in MTIME comparator logic (interrupt condition mtime >= mtimecmp was not always evaluated correctly)
• fixed CPU's IRQ prioritization: (re-)enter debug mode interrupts have to be evaluated before all other interrupts
• fixed missing IRQ signal assignments (MSW and XIRQ) in AXI4-lite top wrapper

💡 Updates and New Features

• ⚠️ split processor-internal memory VHDL sources (IMEM and DMEM) into separated files (PR #151):
  • entity-only (rtl/core/neorv32_*mem.entity.vhd) and default architecture-only (rtl/core/mem/neorv32_*mem.default.vhd)
• ⚠️ Zifencei extension is now required for the on-chip debugger; executing fence.i without having the Zifencei extension enabled will now cause an illegal instruction exception
• ⚠️ major change of low-level hardware access (memory-mapped registers) PR #158:
  • now using struct-based access concept (IO module = struct, interface registers = members of struct) instead of #define single-pointers, format: NEORV32_<module_name>.<register_name>
  • renamed all control registers and bits from *CT* to *CTRL*
  • added sw/lib/include/neorv32_legacy.h compatibility layer (maps deprecated "defines" to according structs, provides old control register/bit names)
• ⚠️ reworked CPU trap/exception system (in order to comply with RISC-V specs.):
  • removed non-maskable interrupt (NMI, top signal nm_irq_i)
  • reworked CPU trap prioritization (sync exceptions before debug mode enter exceptions before async exceptions)
  • RISC-V interrupts (MTI, MSI, MEI) are now high-level-triggered and require to stay asserted until they are explicitly acknowledged
• started porting the task management system to PyDoit PR #110
• misa, mip and mtval CSRs are read-only; however, write accesses to these CSRs do not raise an illegal instruction exception (anymore)
• added menvcfg[h] CSRs (only available if U ISA extension is enabled; not used yet - hardwired to zero, but required by RISC-V spec.)
• reworked CPU/software handshake of external interrupt controller XIRQ to avoid "external IRQ -> CPU IRQ" race conditions
• if CPU_CNT_WIDTH generic (actual width of [m]cycle and [m]instret counters) is less than 64 the remaining bits are now just hardwired to zero ignoring any write access instead of causing an exception

✔️ Pull Requests and Issues

Merged pull requests:

• #150 [sim] create subdir 'simple', avoid making a local copy of 'sw' and 'sim'
• #151 [rtl/core] split dmem/imem entities and architectures to separated files
• #152 Adding NEORV32 Qsys/Platform Designer component and AvalonMM Master Interface wrapper
• #154 fix typo wb_mem_a.cyc on sim example
• #156 [docs/userguide] update section 'Simulating the Processor'
• #158 rework low-level hardware access
• #159 [setups/osflow/filesets] do not provide default NEORV32_MEM_SRC, require it to be explicitly set
• #160 add pydoit to custom dockerfiles
• #161 [containers] update from Debian Buster to Debian Bullseye
• #162 [doit] add initial doit file; add task DeployToGitHubPages
• #163 [doit] add task Documentation
• #164 [doit] add task RunRISCVArchitectureTests
• #165 [doit] add task BuildAndInstallSoftwareFrameworkTests
• #166 docs: datasheet: soc_sysinfo: fix NEORV32_SYSINFO.SOC bits description

Closed issues:

• #153 simulation cycle signal of instruction memory