v1.6.1

This list shows the main core changes since the last release. See the project's changelog for more information.

🐛 Bug Fixes

• fixed bug in MTIME comparator logic (interrupt condition mtime >= mtimecmp was not always evaluated correctly)
• fixed CPU's IRQ prioritization: (re-)enter debug mode interrupts have to be evaluated before all other interrupts
• fixed missing IRQ signal assignments (MSW and XIRQ) in AXI4-lite top wrapper

💡 Updates and New Features

• ⚠️ split processor-internal memory VHDL sources (IMEM and DMEM) into separated files (PR #151):
  • entity-only (rtl/core/neorv32_*mem.entity.vhd) and default architecture-only (rtl/core/mem/neorv32_*mem.default.vhd)
• ⚠️ Zifencei extension is now required for the on-chip debugger; executing fence.i without having the Zifencei extension enabled will now cause an illegal instruction exception
• ⚠️ major change of low-level hardware access (memory-mapped registers) PR #158:
  • now using struct-based access concept (IO module = struct, interface registers = members of struct) instead of #define single-pointers, format: NEORV32_<module_name>.<register_name>
  • renamed all control registers and bits from *CT* to *CTRL*
  • added sw/lib/include/neorv32_legacy.h compatibility layer (maps deprecated "defines" to according structs, provides old control register/bit names)
• ⚠️ reworked CPU trap/exception system (in order to comply with RISC-V specs.):
  • removed non-maskable interrupt (NMI, top signal nm_irq_i)
  • reworked CPU trap prioritization (sync exceptions before debug mode enter exceptions before async exceptions)
  • RISC-V interrupts (MTI, MSI, MEI) are now high-level-triggered and require to stay asserted until they are explicitly acknowledged
• started porting the task management system to PyDoit PR #110
• misa, mip and mtval CSRs are read-only; however, write accesses to these CSRs do not raise an illegal instruction exception (anymore)
• added menvcfg[h] CSRs (only available if U ISA extension is enabled; not used yet - hardwired to zero, but required by RISC-V spec.)
• reworked CPU/software handshake of external interrupt controller XIRQ to avoid "external IRQ -> CPU IRQ" race conditions
• if CPU_CNT_WIDTH generic (actual width of [m]cycle and [m]instret counters) is less than 64 the remaining bits are now just hardwired to zero ignoring any write access instead of causing an exception

✔️ Pull Requests and Issues

Merged pull requests:

• #150 [sim] create subdir 'simple', avoid making a local copy of 'sw' and 'sim'
• #151 [rtl/core] split dmem/imem entities and architectures to separated files
• #152 Adding NEORV32 Qsys/Platform Designer component and AvalonMM Master Interface wrapper
• #154 fix typo wb_mem_a.cyc on sim example
• #156 [docs/userguide] update section 'Simulating the Processor'
• #158 rework low-level hardware access
• #159 [setups/osflow/filesets] do not provide default NEORV32_MEM_SRC, require it to be explicitly set
• #160 add pydoit to custom dockerfiles
• #161 [containers] update from Debian Buster to Debian Bullseye
• #162 [doit] add initial doit file; add task DeployToGitHubPages
• #163 [doit] add task Documentation
• #164 [doit] add task RunRISCVArchitectureTests
• #165 [doit] add task BuildAndInstallSoftwareFrameworkTests
• #166 docs: datasheet: soc_sysinfo: fix NEORV32_SYSINFO.SOC bits description

Closed issues:

• #153 simulation cycle signal of instruction memory

v1.6.0

This list shows the main core changes since the last release. See the project's changelog for more information.

🐛 Bug Fixes

• fixed bug in mret instruction (caused an exception if user mode was not implemented)
• fixed missing flash_sdi_i in Radiant-related example setups and processor wrappers

💡 Updates and New Features

• ⚠️ removed USER_CODE generic and according SYSINFO register
• ⚠️ removed custom mzext CSR; moved all information flags to new SYSINFO_CPU register in SYSINFO module
• ⚠️ removed mstatus.SD and mstatus.FS CSR flags
• added new designated test setups: rtl/test_setups, 📚 UG: General Hardware Setup
• fixed Zifencei test of riscv-arch-test port
• added flags to SYSINFO module to check FAST_SHIFT_EN and FAST_MUL_EN generics by software
• ✨ added support for RISC-V Zbb extension (basic bit-manipulation operations); support via intrinsic library

✔️ Pull Requests and Issues

Merged pull requests:

• #136 [proposal] add rtl/test_setups
• #137 Move osflow examples
• #139 Added AlhambraII and ULX3S boards
• #142 split rtl/templates folder
• #143 SYSINFO documentation fixups
• #144 [setups] add terasic cyclone v starter kit
• #149 [setup/osflow/boards/index.mk] do not set GHDL_PLUGIN_MODULE unconditionally

Closed issues:

• #128 Do we really need wrappers for the top entity?
• #132 Cannot fit on XC6SLX9
• #135 Missing documentation and Makefiles for iCE40 and ECP5 Lattice FPGAs
• #138 common/common.mk : 144 main.elf Error 1
• #148 Windows workflow keeps failing

v1.5.9

This list shows the main core changes since the last release. See the project's changelog for more information.

🐛 Bug Fixes

• ⚠️ fixed major bug in CPU interrupt system: interrupts during memory accesses broke those memory accesses leading to undefined behavior
• fixed bug in E ISA extension that prevented the extension to be actually enabled
• fixed bug in linker script (#134): missing constant data section
• fixed bug in AXI4-Lite wrapper (#133) that caused failure of Vivado packaging
• fixed bug in execution of xRET instructions (trapping of MRET and DRET when not in according mode was missing)

💡 Updates and New Features

• ⚠️ top entity machine-level interrupts now trigger on rising edges (mext_irq_i, msw_irq_i, mtime_irq_i, nm_irq_i)
• exposed advanced external bus interface configuration options as new top entity generics (moved from package constants): MEM_EXT_PIPE_MODE, MEM_EXT_BIG_ENDIAN, MEM_EXT_ASYNC_RX
• added mstatus.TW CSR flag (to allow execution of wfi in user machine mode)
• added mstatus.FS and mstatus.SD CSR bits to control the state of the FPU (Zfinx extension)
• added mconfigptr CSR (not actually used yet, read-only, always zero)
• reworked CPU register file ("implementation" of zero register)
• clean-up of processor top's generic and signals default values

✔️ Pull Requests and Issues

Merged pull requests:

• none

Closed issues:

• #133 Problems generating a Vivado-Block Design
• #134 Missing memory section for .rodata in neorv32.ld

v1.5.8

This list shows the main core changes since the last release. See the project's changelog for more information.

🐛 Bug Fixes

• fixed bug in custom functions subsystem CFS: address map layout overlapping
• fixed minor bug in FIFO component (setups with FIFO_DEPTH = 1 caused mapping issues)

💡 Updates and New Features

• added RISC-V Zmmul ISA extension (subset of M extension: integer HW multiplier, but no HW divider; intended for area-constrained setups)
• bootloader is more independent of HW configuration (no need for UART, MTIME, GPIO anymore); added several options to customize default bootloader
• ⚠️ removed top's fast IRQ (FIRQ) inputs soc_firq_i
• ⚠️ removed numerically-controller oscillator module (NCO)
• added new processor module stream link interface (SLINK) providing up to 8 independent RX and TX links
• increased GPIO port size from 32-bit to 64-bit
• added new processor module external interrupt controller (XIRQ) providing up to 32 processor-external interrupt request lines
• new performance-vs-ares configuration generic: CPU_IPB_ENTRIES defines size of CPU's instruction prefetch buffer
• reworked NEOLED module: IRQ now uses fifo half-full fill level; added option to send LED RESET command as explicit FIFO command
• (re-)added mstatush CSR (hardwired to zero)
• minor logic optimizations to reduce area requirements and switching activity and to shorten critical path

✔️ Pull Requests and Issues

Merged pull requests:

• #89 Make uart_rx a verification component
• #90 Make uart_rx a VUnit verification component. Step 4.
• #92 sim: update readme
• #93 [setups/vivado] arty-a7-test-setup: define multiple filesets, set board, set language
• #95 Add loopback test for SLINK
• #98 OrangeCrab
• #99 osflow rework
• #100 [docs] move Makefile from project root to subdir 'docs'
• #104 [setups/osflow] cleanup
• #107 [setups/osflow] update OrangeCrab constraints file
• #109 riscv-arch-test script cleanup
• #114 use RISCV_PREFIX instead of RISCV_TOOLCHAIN
• #116 [ci] add workflow 'Containers'
• #117 mv riscv-arch-test sw/sig-arch-test
• #118 [sw/example] add common.mk
• #119 [riscv-arch-test] measure execution time of each test
• #120 [sim/ghdl] use --workdir=build
• #123 [docs] update references to isa-test
• #124 Split ISA test suites in multiple jobs and rework makefiles
• #125 Fix source/sink mixup in SLINK docs
• #127 [ci/windows] fix RISCV_PREFIX

Closed issues:

• #77 Use ProcessorTop templates in non osflow examples
• #97 Having trouble building the iCESugar example
• #106 Constraints file for OrangeCrab r0.2
• #108 question: Is the prebuilt build support rv32IMAC ISA extension or just rv32imc?
• #122 Add halfway interrupts for SLINK interface

v1.5.7

This list shows the main changes since the last release. See the project's changelog for more information.

🐛 Bug Fixes

• fixed bug in instruction cache flush/re-sync logic (via fence.i instruction) - cache might have missed a re-sync request in some cases
• fixed bug in debugger park loop: instruction cache re-sync (fence.i) was missing - caused debugger to execute obsolete code from program buffer

💡 Updates and New Features

• fixed endiannes inconsistencies: processor/CPU is little-endian
• ⚠️ removed TINY_SHIFT_EN generic; CPU shifter is implemented as iterative single-bit shift by default
• ⚠️ reworked boot configuration
  • removed MEM_INT_IMEM_ROM generic; processor-internal IMEM is implemented as ROM if internal IMEM is enabled (MEM_INT_IMEM_EN = true) and internal bootloader is disabled (INT_BOOTLOADER_EN = false)
• ⚠️ removed option to grant user-level access to HPM counters (removed according mcounteren CSR bits)
• increased processor-internal IO size (from 256 bytes to 512 bytes)
  • relocated base address of CFS module
• number of PWM channels is now configured via IO_PWM_NUM_CH generic (0=none at all, max 60)
• ⚠️ CPU B extension has been (temporarily) removed from the core
• CPU_CNT_WIDTH and HPM_CNT_WIDTH generics can now also be zero to exclude CPU core counters (cycle & instret) and HPM counters
• minor logic optimizations to reduce area requirements and switching activity and to shorten critical path

✔️ Pull Requests and Issues

Merged pull requests:

• #47 Update CI to use VUnit for running VHDL testbenches
• #48 Introduce VUnit logging and checking
• #53 docs: split User Guide
• #54 [ci] cleanup
• #59 Add examples
• #60 [docs] add attrs.adoc and attrs.main.adoc
• #61 Reorganise setups
• #63 Add Fomu
• #64 [sim] split UART logging component, make self-checking
• #65 Add VUnit
• #66 [sim/VUnit] support CLI argument for selecting the expected UART responses
• #67 rename logical library 'iCE40UP' to 'iCE40'
• #69 VUnit checking
• #71 Add MSYS2 jobs to continuous integration workflows
• #72 [ci/riscv-arch-test] make test script executable
• #73 [sim] make ghdl_sim.sh executable
• #74 [ci/generate-job-matrix] fix UPduino_v3 artifact (bitstream) extension
• #75 iCESugar
• #76 [setups/examples] add iCESugar Minimal
• #79 add mailmap
• #80 Added option to print a selected subset of information from processor…
• #82 [sim] use custom VUnit loggers for better verbosity control
• #83 [setups/osflow] support optionally using Verilog sources and add Fomu MixedLanguage example
• #84 [setups/osflow/iCESugar] update PCF

Closed issues:

• #50 Endianness inconsistency
• #58 mtime_o could be instable
• #62 Processor Boot Concept
• #70 Passing argument to ghdl_sim.sh - bug?

📚 Documentation

• reworked data sheet section Address Space
  • added section Memory Configuration
  • added section Boot Configuration
• reworked and updated complete User Guide
• typo and layout fixes