v1.10.5

What's Changed

• [rtl] signal renamings and cleanups to make the code more readable by @stnolting in #1026
• 🐛 fix minor bug in FPU MUL instruction by @stnolting in #1028
• [rtl] remove redundant prog_buf by @NikLeberg in #1030
• [rtl] fix generate spelling by @NikLeberg in #1031
• [cpu] rework ALU instruction decoding and CPU co-processor interface by @stnolting in #1032
• ✨ [cpu] add support for RISC-V scalar cryptography ISA extensions by @stnolting in #1033
• Fix typo trap table by @BEforlin in #1035
• Add Zkt ISA extension by @stnolting in #1036
• ✨ add support for RISC-V Zbkb ISA extension by @stnolting in #1037
• ✨ add support for RISC-V Zbkc ISA extension by @stnolting in #1038
• Add Zkn ISA extension by @stnolting in #1039
• ✨ add support for RISC-V Zks* ISA extensions by @stnolting in #1040
• ⚠️ Rename CPU ISA configuration generics by @stnolting in #1041
• ⚠️ split B ISA extension into individual sub-extensions by @stnolting in #1044

New Contributors

• @BEforlin made their first contribution in #1035

Full Changelog: v1.10.4...v1.10.5