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⚠️ split B ISA extension into individual sub-extensions #1044

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merged 9 commits into from
Oct 1, 2024

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@stnolting stnolting commented Sep 30, 2024

The RISC-V "bit manipulation" (B) ISA extensions consists of three individual sub-extensions. This PR splits the core's B extension so users can specify which sub-extension they really need (improving hardware efficiency).

  • Zba: shifted-add bit manipulation instructions; enabled via RISCV_ISA_Zba
  • Zbb: basic bit manipulation instructions; enabled via RISCV_ISA_Zbb
  • Zbs: single-bit bit manipulation instructions; enabled via RISCV_ISA_Zbs

Hence, B = Zba + Zbb + Zbs.

@stnolting stnolting added HW Hardware-related customization Tailoring the core to your needs labels Sep 30, 2024
@stnolting stnolting self-assigned this Sep 30, 2024
@stnolting stnolting marked this pull request as ready for review September 30, 2024 21:29
@stnolting stnolting merged commit a7f56cc into main Oct 1, 2024
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@stnolting stnolting deleted the b_isa_extension branch October 1, 2024 13:20
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