[cpu] rework ALU instruction decoding and CPU co-processor interface

[stnolting]

This is a massive rework of the CPU instruction decoding logic that replaces the centralized instruction decoding (inside the control unit) by a "split" decoding.

Only the basic rv32 register-register / register-immediate ALU instruction (alu/alui opcode space) are decoded inside the control unit. All further instructions (including shift operation) are forwarded to the CPU co-processors. If no co-processor generates a response within a bound amount of time the instruction is considered "illegal" (raising an exception). Therefore, each co-processor has to decode all relevant instructions locally.

This change aims to reduce hardware complexity and to make the code base easier to understand and maintain.