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[AMD] Enable mamba-extra-buffer for Qwen3.5 on ROCm - #32552
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nemanjaudovic wants to merge 27 commits into
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nemanjaudovic wants to merge 27 commits into
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… NVFP4 online quantization (sgl-project#30397) (sgl-project#30424) Co-authored-by: Brayden Zhong <b8zhong@uwaterloo.ca> Co-authored-by: Brayden Zhong <brayden@radixark.ai>
… NVILA weight loading (sgl-project#30400) (sgl-project#30425) Co-authored-by: Brayden Zhong <b8zhong@uwaterloo.ca> Co-authored-by: Brayden Zhong <brayden@radixark.ai>
…TP: clamp padded-row seq_lens to >= 0 (sgl-project#30378) (sgl-project#30427) Co-authored-by: DarkSharpness <76582120+DarkSharpness@users.noreply.github.com> Co-authored-by: ziyi.xu <ziyi.xu@radixark.ai> Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
…er by default for large prefill chunks (sgl-project#30140) (sgl-project#30436) Co-authored-by: YAMY <74099316+YAMY1234@users.noreply.github.com>
…ensor contiguous (sgl-project#27926) (sgl-project#30449) Co-authored-by: Kaixi <matteochen3@gmail.com> Co-authored-by: liqichao <liqichao@baidu.com> Co-authored-by: chenbong <bhchen@stu.xmu.edu.cn>
…#30439) (sgl-project#30465) Co-authored-by: Baizhou Zhang <sobereddiezhang@gmail.com>
…te all output slots on tie overflow (sgl-project#30512) (sgl-project#30559) Co-authored-by: Jimmy Shong <69131491+Jiminator@users.noreply.github.com> Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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…t kernel in decode graph when not recording (sgl-project#30302) (sgl-project#30726) Co-authored-by: Rita Brugarolas <Rita.BrugarolasBrufau@amd.com>
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…oss PD and CUDA graph replay (sgl-project#30839) (sgl-project#31083) Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
…th prefill CP (sgl-project#30992) (sgl-project#31106) Co-authored-by: zRzRzRzRzRzRzR <Yuxuan.Zhang2@liverpool.ac.uk>
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Signed-off-by: nemanjaudovic <nudovic@amd.com>
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September 15, 2026 02:52
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Ports upstream #30359 to amd_march: adds
is_hip()to the_validate_mamba_extra_bufferplatform check so hybrid-mamba models (Qwen3.5 / Qwen3-Next)can use the extra_buffer radix-cache strategy on ROCm instead of asserting at startup. The
required kernels (FLA chunk-scan, selective_state_update) are Triton and AMD-aware; the assert
was a validated-platform whitelist, not a hard limit.
CI States
Latest PR Test (Base): ❌ Run #34828715619
Latest PR Test (Extra): ❌ Run #34828715349
Latest PR Test (AMD ROCm 10): ➖ No AMD PR run found for this commit.