[AMD] fix dsv4 indexer dtype dispatch on gfx950 - #29479
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billishyahao
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Jun 27, 2026
| if is_hip(): | ||
| if is_fp8_fnuz(): | ||
| FP8_DTYPE = torch.float8_e4m3fnuz | ||
| FP8_MAX = torch.finfo(FP8_DTYPE).max |
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@billishyahao cross repos, we use abs up to 224.0, not 240.0 as FP8_MAX for e4m3fnuz.
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Get it! I re-checked the usage and FP8_MAX is invoked within indexer.py so I removed this part totally.
This was referenced Jul 3, 2026
HaiShaw
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Co-authored-by: HAI <hixiao@gmail.com> (cherry picked from commit 336b64e)
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Co-authored-by: HAI <hixiao@gmail.com> (cherry picked from commit 336b64e)
This was referenced Jul 10, 2026
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…h on gfx950 (sgl-project#29479) (sgl-project#30725) Co-authored-by: billishyahao <bill.he@amd.com> Co-authored-by: HAI <hixiao@gmail.com>
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Co-authored-by: HAI <hixiao@gmail.com>
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Motivation
The DeepSeek-V4 indexer and the unified-KV paged-decode kernel selected their FP8 data type with
is_hip(), which hardcodestorch.float8_e4m3fnuzfor all AMD GPUs. This is only correct on CDNA3 (gfx942). This PR aligns the dtype so the dispatch is correct on gfx950 (and unchanged on gfx942 / NVIDIA).Modifications
python/sglang/srt/layers/attention/dsv4/indexer.pyFP8_DTYPE/FP8_MAXviais_fp8_fnuz()instead ofis_hip().is_fp8_fnuzfromsglang.srt.layers.quantization.fp8_kernel; drop thenow-unused
is_hipimport.python/sglang/srt/layers/attention/dsv4/unified_kv_kernels/paged_decode.py_FP8_DTYPEviais_fp8_fnuz()instead of the hardcodedtorch.float8_e4m3fnuz; add the import and update the storage comment.Accuracy Tests
GSM8K on gfx950 (MI355) with DeepSeek-V4-Pro,
tp=8,--kv-cache-dtype fp8_e4m3,--attention-backend dsv4:Speed Tests and Profiling
Checklist
Review and Merge Process
/tag-and-rerun-ci,/tag-run-ci-label,/rerun-failed-ciCI States
Latest PR Test (Base): ❌ Run #29009248782
Latest PR Test (Extra): ❌ Run #29009248687