Update support for openpiton #1
Commits on Apr 5, 2022
Commits on May 2, 2022
Commits on May 11, 2022
Commits on May 12, 2022
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cva6.sv: change RVFI exception signal (openhwgroup#873)
Signed-off-by: Guillaume Chauvon <[email protected]>
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Add support for "high" counter CSRs in 32-bit mode (openhwgroup#847)
* Add support for "high" counter CSRs in 32-bit mode In 32bit mode MCYCLEH, MINSTRETH, CYCLEH, TIMEH and INSTRETH are used to return the most significant 32-bit value of the counters which are now always 64-bit wide. Signed-off-by: Steffen Persvold <[email protected]> * Enable writing of MCYCLEH and MINSTRETH CSRs Signed-off-by: Steffen Persvold <[email protected]>
Commits on May 30, 2022
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Fix tc_srams paths (openhwgroup#892)
* cva6_synth.tcl: fix set_input_delay and set_output_delay tc_sram paths * ariane_tb.cpp;.sv: [Fix tc_srams] change path for user memory preload Signed-off-by: Guillaume Chauvon <[email protected]> Co-authored-by: Jean-Roch Coulon <[email protected]>
Commits on Jun 10, 2022
Commits on Jun 16, 2022
Commits on Jun 28, 2022
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FPGA: Add scripts to boot linux fpga (openhwgroup#924)
Signed-off-by: Guillaume Chauvon<[email protected]>
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Cvvdev/dev/formating4 (openhwgroup#920)
Several format cleanings: - split load_store_unit.sv to create lsu_bypass.sv - add several "begin" and "end"
Commits on Jun 30, 2022
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Enable CVXIF for target cv32a60X and add renaming for cvxif when usin…
…g 3 operands (openhwgroup#925) * re_name.sv: add condition related to CVXIF to rename 3rd operand * cv32a60x_pkg.sv: set CVXIFEn to 1
Commits on Jul 5, 2022
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Adding a Bug issue template (openhwgroup#930)
* Create bug.yaml * Update bug.yaml - Case consistency * Spelling mistakes
Commits on Jul 6, 2022
Commits on Jul 8, 2022
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Fix exception type on PMP check during PTW (openhwgroup#908)
Fixes openhwgroup#906 According to the spec: > If accessing pte violates a PMA or PMP check, raise an access-fault > exception corresponding to the original access type. Found by @Phantom1003 and @ProjectDimlight Signed-off-by: Moritz Schneider <[email protected]>
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Associated PRs in task.yaml (openhwgroup#929)
* Removing CVA6-SDK from task.yaml * Associated PRs in task.yaml This commit provide a new textarea to fill links to PRs used to complete the task. * Create bug.yaml * Update bug.yaml - Case consistency Co-authored-by: JeanRochCoulon <[email protected]>
Commits on Jul 20, 2022
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decoder.sv: fix sfence.vma when rs1 != 0 (openhwgroup#933)
unlike other instructions with minor opcode == PRIV, SFENCE.VMA do not check for rs1 != 0. Only check for rd !=0 to raise illegal instruction Signed-off-by: Guillaume Chauvon <[email protected]>
Commits on Aug 1, 2022
Commits on Aug 16, 2022
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cvxif_fu.sv: add register to hold illegal instruction information (op…
…enhwgroup#939) It avoids that result from cvxif and illegal instruction use wb bus at the same time
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perf_counters.sv: unimplemented mhpmcounters shall be read-only 0 (op…
…enhwgroup#940) see The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 20211203 3.1.1 Hardware Performance Monitor All counters should be implemented, but a legal implementation is to make both the counter and its corresponding event selector be read-only 0. Signed-off-by: André Sintzoff <[email protected]>
