Update support for openpiton

.github/ISSUE_TEMPLATE/bug.yaml

@@ -0,0 +1,18 @@
+name: CVA6 bug
+description: Create a CVA6 bug
+title: "[BUG] <title>"
+labels: ["Type:Bug"]
+body:
+- type: checkboxes
+  attributes:
+    label: Is there an existing CVA6 bug for this?
+    description: Please search to see if an issue already exist for the bug you need to create
+    options:
+    - label: I have searched the existing bug issues
+      required: true
+- type: textarea
+  attributes:
+    label: Bug Description
+    description: A concise description of the bug
+  validations:
+    required: true

.github/ISSUE_TEMPLATE/task.yaml

@@ -1,11 +1,11 @@
 name: CVA6 Task
-description: Create a CVA6-SDK Project Task
+description: Create a CVA6 Project Task
 title: "[TASK] <title>"
 labels: ["task"]
 body:
 - type: checkboxes
   attributes:
-    label: Is there an existing CVA6-SDK task for this?
+    label: Is there an existing CVA6 task for this?
     description: Please search to see if a task issue already exists for the task you need to create
     options:
     - label: I have searched the existing task issues
@@ -22,6 +22,10 @@ body:
     description: What are the criteria for completion of this task?
   validations:
     required: true
+- type: textarea
+  attributes:
+    label: Associated PRs
+    description: Use this area to provide a link to PRs used to complete this task.
 - type: markdown
   attributes:
     value: |

.gitlab-ci.yml

@@ -40,17 +40,18 @@ include:
 
 workflow:
   rules:
-    - if: '$CI_COMMIT_REF_NAME =~ /^master.*/ || $CI_COMMIT_REF_NAME =~ /^hotfix.*/ || $CI_COMMIT_REF_NAME =~ /^rc.*/'
+    - if: '$CI_WEIGHT == "forced"' #bypass workflow
+    - if: '$CI_COMMIT_REF_NAME =~ /^master.*|^hotfix.*|^rc.*|^github-pr.*/'
       variables:
         CI_WEIGHT: "full"
-    - if: '$CI_COMMIT_REF_NAME =~ /^dev.*/ || $CI_COMMIT_REF_NAME =~ /^feature.*/'
+    - if: '$CI_COMMIT_REF_NAME =~ /^dev.*|^feature.*/'
       variables:
-        CI_WEIGHT: "lite"
-    - if: '$CI_COMMIT_REF_NAME =~ /^cvvdev\/master.*/ || $CI_COMMIT_REF_NAME =~ /^cvvdev\/hotfix.*/ || $CI_COMMIT_REF_NAME =~ /^cvvdev\/rc.*/'
+        CI_WEIGHT: "short"
+    - if: '$CI_COMMIT_REF_NAME =~ /^cvvdev\/master.*|^cvvdev\/hotfix.*|^cvvdev\/rc.*/'
       variables:
         CI_WEIGHT: "full"
         CORE_V_VERIF_BRANCH: $CI_COMMIT_REF_NAME
-    - if: '$CI_COMMIT_REF_NAME =~ /^cvvdev\/dev.*/ || $CI_COMMIT_REF_NAME =~ /^cvvdev\/feature.*/'
+    - if: '$CI_COMMIT_REF_NAME =~ /^cvvdev\/dev.*|^cvvdev\/feature.*/'
       variables:
         CI_WEIGHT: "lite"
         CORE_V_VERIF_BRANCH: $CI_COMMIT_REF_NAME

Flist.ariane

@@ -15,139 +15,150 @@
 // Author: Michael Schaffner <[email protected]>, ETH Zurich
 // Date: 15.08.2018
 // Description: File list for OpenPiton flow
-+incdir+src/common_cells/include/
-+incdir+src/util/
-include/riscv_pkg.sv
-src/riscv-dbg/src/dm_pkg.sv
-include/ariane_pkg.sv
-src/common_cells/src/deprecated/rrarbiter.sv
-src/common_cells/src/deprecated/fifo_v1.sv
-src/common_cells/src/deprecated/fifo_v2.sv
-src/common_cells/src/fifo_v3.sv
-src/common_cells/src/lfsr_8bit.sv
-src/common_cells/src/lzc.sv
-src/common_cells/src/rr_arb_tree.sv
-src/common_cells/src/rstgen_bypass.sv
-src/common_cells/src/cdc_2phase.sv
-src/common_cells/src/shift_reg.sv
-src/common_cells/src/unread.sv
-src/common_cells/src/popcount.sv
-src/common_cells/src/exp_backoff.sv
-src/register_interface/src/apb_to_reg.sv
-src/register_interface/src/reg_intf_pkg.sv
-src/register_interface/src/reg_intf.sv
-src/fpu/src/fpnew_pkg.sv
-src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
-src/fpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv
-src/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv
-src/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv
-src/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv
-src/fpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv
-src/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
-src/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
-src/fpu/src/fpnew_cast_multi.sv
-src/fpu/src/fpnew_classifier.sv
-src/fpu/src/fpnew_divsqrt_multi.sv
-src/fpu/src/fpnew_fma_multi.sv
-src/fpu/src/fpnew_fma.sv
-src/fpu/src/fpnew_noncomp.sv
-src/fpu/src/fpnew_opgroup_block.sv
-src/fpu/src/fpnew_opgroup_fmt_slice.sv
-src/fpu/src/fpnew_opgroup_multifmt_slice.sv
-src/fpu/src/fpnew_rounding.sv
-src/fpu/src/fpnew_top.sv
-src/axi/src/axi_pkg.sv
-tb/ariane_soc_pkg.sv
-tb/ariane_axi_soc_pkg.sv
-include/ariane_axi_pkg.sv
-include/wt_cache_pkg.sv
-include/std_cache_pkg.sv
-include/axi_intf.sv
-include/instr_tracer_pkg.sv
-src/util/instr_tracer_if.sv
-src/util/instr_tracer.sv
-src/util/sram.sv
-src/fpga-support/rtl/SyncSpRamBeNx64.sv
-src/dromajo_ram.sv
-src/axi_mem_if/src/axi2mem.sv
-src/tech_cells_generic/src/pulp_clock_gating.sv
-src/tech_cells_generic/src/cluster_clock_inverter.sv
-src/tech_cells_generic/src/pulp_clock_mux2.sv
-src/pmp/src/pmp.sv
-src/pmp/src/pmp_entry.sv
-src/axi_adapter.sv
-src/alu.sv
-src/fpu_wrap.sv
-src/ariane.sv
-src/branch_unit.sv
-src/compressed_decoder.sv
-src/controller.sv
-src/csr_buffer.sv
-src/csr_regfile.sv
-src/decoder.sv
-src/ex_stage.sv
-src/instr_realign.sv
-src/frontend/btb.sv
-src/frontend/bht.sv
-src/frontend/ras.sv
-src/frontend/instr_scan.sv
-src/frontend/instr_queue.sv
-src/frontend/frontend.sv
-src/id_stage.sv
-src/issue_read_operands.sv
-src/issue_stage.sv
-src/load_unit.sv
-src/load_store_unit.sv
-src/mmu_sv39/mmu.sv
-src/mmu_sv32/cva6_mmu_sv32.sv
-src/mult.sv
-src/multiplier.sv
-src/serdiv.sv
-src/perf_counters.sv
-src/ptw.sv
-src/ariane_regfile_ff.sv
-src/re_name.sv
-src/scoreboard.sv
-src/store_buffer.sv
-src/amo_buffer.sv
-src/store_unit.sv
-src/tlb.sv
-src/commit_stage.sv
-src/cache_subsystem/wt_dcache_ctrl.sv
-src/cache_subsystem/wt_dcache_mem.sv
-src/cache_subsystem/wt_dcache_missunit.sv
-src/cache_subsystem/wt_dcache_wbuffer.sv
-src/cache_subsystem/wt_dcache.sv
-src/cache_subsystem/cva6_icache.sv
-src/cache_subsystem/wt_l15_adapter.sv
-src/cache_subsystem/wt_cache_subsystem.sv
-src/clint/clint.sv
-src/clint/axi_lite_interface.sv
-src/riscv-dbg/src/dm_csrs.sv
-src/riscv-dbg/src/dm_mem.sv
-src/riscv-dbg/src/dm_top.sv
-src/riscv-dbg/src/dmi_cdc.sv
-src/riscv-dbg/src/dmi_jtag.sv
-src/riscv-dbg/src/dm_sba.sv
-src/riscv-dbg/src/dmi_jtag_tap.sv
-src/riscv-dbg/debug_rom/debug_rom.sv
-openpiton/ariane_verilog_wrap.sv
-openpiton/riscv_peripherals.sv
-openpiton/bootrom/baremetal/bootrom.sv
-openpiton/bootrom/linux/bootrom_linux.sv
-src/rv_plic/rtl/rv_plic_target.sv
-src/rv_plic/rtl/rv_plic_gateway.sv
-src/rv_plic/rtl/plic_regmap.sv
-src/rv_plic/rtl/plic_top.sv
-fpga/src/axi2apb/src/axi2apb_wrap.sv
-fpga/src/axi2apb/src/axi2apb.sv
-fpga/src/axi2apb/src/axi2apb_64_32.sv
-fpga/src/axi_slice/src/axi_w_buffer.sv
-fpga/src/axi_slice/src/axi_b_buffer.sv
-fpga/src/axi_slice/src/axi_slice_wrap.sv
-fpga/src/axi_slice/src/axi_slice.sv
-fpga/src/axi_slice/src/axi_single_slice.sv
-fpga/src/axi_slice/src/axi_ar_buffer.sv
-fpga/src/axi_slice/src/axi_r_buffer.sv
-fpga/src/axi_slice/src/axi_aw_buffer.sv
++incdir+common/submodules/common_cells/include/
++incdir+common/local/util/
++incdir+corev_apu/register_interface/include/
 
+core/include/cv64a6_imafdc_sv39_config_pkg.sv
+core/include/riscv_pkg.sv
+corev_apu/riscv-dbg/src/dm_pkg.sv
+core/include/ariane_pkg.sv
+corev_apu/tb/ariane_soc_pkg.sv
+corev_apu/axi/src/axi_pkg.sv
+core/include/ariane_axi_pkg.sv
+core/include/wt_cache_pkg.sv
+core/include/axi_intf.sv
+core/fpu/src/fpnew_pkg.sv
+core/include/cvxif_pkg.sv
+common/submodules/common_cells/src/cf_math_pkg.sv
+core/include/instr_tracer_pkg.sv
+core/cvxif_example/include/cvxif_instr_pkg.sv
+corev_apu/rv_plic/rtl/rv_plic_reg_pkg.sv
+common/local/util/sram.sv
+common/submodules/common_cells/src/deprecated/rrarbiter.sv
+common/submodules/common_cells/src/deprecated/fifo_v1.sv
+common/submodules/common_cells/src/deprecated/fifo_v2.sv
+common/submodules/common_cells/src/fifo_v3.sv
+common/submodules/common_cells/src/shift_reg.sv
+common/submodules/common_cells/src/lfsr_8bit.sv
+common/submodules/common_cells/src/lfsr.sv
+common/submodules/common_cells/src/lzc.sv
+common/submodules/common_cells/src/exp_backoff.sv
+common/submodules/common_cells/src/rr_arb_tree.sv
+common/submodules/common_cells/src/rstgen_bypass.sv
+common/submodules/common_cells/src/cdc_2phase.sv
+common/submodules/common_cells/src/unread.sv
+common/submodules/common_cells/src/popcount.sv
+corev_apu/axi_mem_if/src/axi2mem.sv
+corev_apu/src/tech_cells_generic/src/deprecated/cluster_clk_cells.sv
+corev_apu/src/tech_cells_generic/src/deprecated/pulp_clk_cells.sv
+common/local/util/tc_sram_wrapper.sv
+corev_apu/src/tech_cells_generic/src/rtl/tc_sram.sv
+corev_apu/src/tech_cells_generic/src/rtl/tc_clk.sv
+core/axi_adapter.sv
+core/alu.sv
+core/fpu_wrap.sv
+core/ariane.sv
+core/cva6.sv
+core/branch_unit.sv
+core/compressed_decoder.sv
+core/controller.sv
+core/csr_buffer.sv
+core/csr_regfile.sv
+core/decoder.sv
+core/ex_stage.sv
+core/frontend/btb.sv
+core/frontend/bht.sv
+core/frontend/ras.sv
+core/frontend/instr_scan.sv
+core/frontend/instr_queue.sv
+core/frontend/frontend.sv
+core/id_stage.sv
+core/instr_realign.sv
+core/issue_read_operands.sv
+core/issue_stage.sv
+core/load_unit.sv
+core/load_store_unit.sv
+core/lsu_bypass.sv
+core/mmu_sv39/mmu.sv
+core/mult.sv
+core/multiplier.sv
+core/serdiv.sv
+core/perf_counters.sv
+core/mmu_sv39/ptw.sv
+core/ariane_regfile_ff.sv
+core/re_name.sv
+core/scoreboard.sv
+core/store_buffer.sv
+core/amo_buffer.sv
+core/store_unit.sv
+core/mmu_sv39/tlb.sv
+core/commit_stage.sv
+core/cache_subsystem/wt_dcache_ctrl.sv
+core/cache_subsystem/wt_dcache_mem.sv
+core/cache_subsystem/wt_dcache_missunit.sv
+core/cache_subsystem/wt_dcache_wbuffer.sv
+core/cache_subsystem/wt_dcache.sv
+core/cache_subsystem/cva6_icache.sv
+core/cache_subsystem/cva6_icache_axi_wrapper.sv
+core/cache_subsystem/wt_l15_adapter.sv
+core/cache_subsystem/wt_cache_subsystem.sv
+corev_apu/clint/clint.sv
+corev_apu/clint/axi_lite_interface.sv
+corev_apu/riscv-dbg/debug_rom/debug_rom.sv
+corev_apu/riscv-dbg/src/dm_csrs.sv
+corev_apu/riscv-dbg/src/dm_mem.sv
+corev_apu/riscv-dbg/src/dm_top.sv
+corev_apu/riscv-dbg/src/dmi_cdc.sv
+corev_apu/riscv-dbg/src/dmi_jtag.sv
+corev_apu/riscv-dbg/src/dm_sba.sv
+corev_apu/riscv-dbg/src/dmi_jtag_tap.sv
+corev_apu/openpiton/riscv_peripherals.sv
+corev_apu/openpiton/ariane_verilog_wrap.sv
+corev_apu/openpiton/bootrom/baremetal/bootrom.sv
+corev_apu/openpiton/bootrom/linux/bootrom_linux.sv
+corev_apu/rv_plic/rtl/rv_plic_target.sv
+corev_apu/rv_plic/rtl/rv_plic_gateway.sv
+corev_apu/rv_plic/rtl/plic_regmap.sv
+corev_apu/rv_plic/rtl/plic_top.sv
+corev_apu/fpga/src/axi2apb/src/axi2apb_wrap.sv
+corev_apu/fpga/src/axi2apb/src/axi2apb.sv
+corev_apu/fpga/src/axi2apb/src/axi2apb_64_32.sv
+corev_apu/fpga/src/axi_slice/src/axi_w_buffer.sv
+corev_apu/fpga/src/axi_slice/src/axi_b_buffer.sv
+corev_apu/fpga/src/axi_slice/src/axi_slice_wrap.sv
+corev_apu/fpga/src/axi_slice/src/axi_slice.sv
+corev_apu/fpga/src/axi_slice/src/axi_single_slice.sv
+corev_apu/fpga/src/axi_slice/src/axi_ar_buffer.sv
+corev_apu/fpga/src/axi_slice/src/axi_r_buffer.sv
+corev_apu/fpga/src/axi_slice/src/axi_aw_buffer.sv
+corev_apu/register_interface/src/apb_to_reg.sv
+corev_apu/register_interface/src/reg_intf.sv
+core/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
+core/fpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv
+core/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv
+core/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv
+core/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv
+core/fpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv
+core/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
+core/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
+core/fpu/src/fpnew_cast_multi.sv
+core/fpu/src/fpnew_classifier.sv
+core/fpu/src/fpnew_divsqrt_multi.sv
+core/fpu/src/fpnew_fma_multi.sv
+core/fpu/src/fpnew_fma.sv
+core/fpu/src/fpnew_noncomp.sv
+core/fpu/src/fpnew_opgroup_block.sv
+core/fpu/src/fpnew_opgroup_fmt_slice.sv
+core/fpu/src/fpnew_opgroup_multifmt_slice.sv
+core/fpu/src/fpnew_rounding.sv
+core/fpu/src/fpnew_top.sv
+core/pmp/src/pmp.sv
+core/pmp/src/pmp_entry.sv
+common/local/util/instr_tracer.sv
+common/local/util/instr_tracer_if.sv
+core/cvxif_example/cvxif_example_coprocessor.sv
+core/cvxif_example/instr_decoder.sv
+common/submodules/common_cells/src/counter.sv
+common/submodules/common_cells/src/delta_counter.sv
+core/cvxif_fu.sv