Adding Support for Zba, Zbb, Zbc and Zbs extensions to CVA6 #878

M-Ijaz-10x · 2022-05-16T12:40:54Z

Introduction

This PR is the continuation of issue-451 and adds support for zba, zbb, zbc and zbs extensions under the wrapper of a compiler directive BITMANIP. These changes have been tested with self-written single instruction tests and using the compliance tests with the core-v-verif infrastructure.

Implementation

Added the support for all the ratified bitmanip extensions as defined under this bitmanip-spec

Zba extension (Address generation instructions)
Zbb extension (Basic bit-manipulation instructions)
Zbc extension (Carry-less multiplication instructions)
Zbs extension (Single-bit instructions)

Integration of bitmanip hardware with cva6

The major changes have been done in the decoder which includes adding the RISC-V Bitmanip opcodes, selecting the Functional Unit from Multiplier and ALU of the Ariane core and implementing design logic for Bitmanip instructions in ALU and Multiplier FUs.

Verification

Assembly Tests

The functionality of each implemented Bitmanip instruction has been verified by running individual assembly tests related to that particular instruction on the updated design.

Core-v-verif environment

The OpenHW group’s core-v-verif verification environment has been modified to support the latest riscv-arch-test infrastructure (PR: Added the support to run latest riscv-arch-tests in core-v-verif CVA6 infrastructure) and used to run the compliance tests (base tests + bitmanip tests) on the updated design. All the required bitmanip tests have successfully passed.

zarubaf

That is really great, thanks for the pull request! Logic looks good to me in general.

The only comments I have are around we handle the inclusion, we usually use parameters for that and try to avoid ifdefs as much as possible. So I've added some comments on how I think we can make this work using only parameters :-) Please do let me know whether there is something unclear from the comments?

Makefile

core/Flist.cv64a6_imafdc_sv39

core/alu.sv

core/multiplier.sv

M-Ijaz-10x · 2022-05-23T19:46:59Z

Thank you @zarubaf for the review.
I have made all the suggested changes. Please let me know if I am missing anything. Thanks :)

zarubaf

Terrific, thanks soo much. Only minor code formatting things and then we are good to go!

core/Flist.cv64a6_imafdc_sv39

core/alu.sv

core/decoder.sv

core/multiplier.sv

JeanRochCoulon · 2022-05-24T09:43:47Z

That's a very great contribution !! Thank for that

As I am not in office in the coming days, I will available to check the PR from June1st to check max frequency, gate count, and functional regression in 32 and 64 bits. I let you know.

M-Ijaz-10x · 2022-05-24T10:05:47Z

That's a very great contribution !! Thank for that

As I am not in office in the coming days, I will available to check the PR from June1st to check max frequency, gate count, and functional regression in 32 and 64 bits. I let you know.

Sure. No Problem!

zarubaf

Everything on my end is green! I will trigger the CI and @JeanRochCoulon you can merge if the PPA is okay for you! Thanks again @M-Ijaz-10x, that is a great contribution!

M-Ijaz-10x · 2022-05-24T12:55:08Z

Everything on my end is green! I will trigger the CI and @JeanRochCoulon you can merge if the PPA is okay for you! Thanks again @M-Ijaz-10x, that is a great contribution!

Happy to contribute. :) Looking forward to contribute more in the future developments.

core/alu.sv

M-Ijaz-10x · 2022-06-01T18:22:10Z

While making the suggested changes on the PR, a bug was overlooked in the design related to exceptions (illegal instruction in the decoder) which was probably causing the tests to fail (CI checks timed-out). This is fixed in the latest commit on this PR. These changes are tested by running RISC-V Compliance tests and Bitmanip tests which came out to be clean now.
@zarubaf Can you please review the new changes and trigger the CI again? Apologies for the inconvenience. Thank you.

JeanRochCoulon · 2022-06-03T10:00:19Z

Hello, thanks again for this contribution. I would request some modifications to make VCS and synthesis work.

By running the Continuous Integration, I get some errors:

During synthesis of 32bits version, Error: ../..//core/csr_regfile.sv:574: Array index out of bounds instret[63:32], valid bounds are [31:0]. (ELAB-298)
During synthesis 32bits, Error: ../..//core/alu.sv:179: Array index out of bounds fu_data_i[63:0], valid bounds are [31:0]. (ELAB-298)
When simulating with VCS, gen_bitmanip name is used twice in multiplier.sv

In another hand, as we would be pleased to enable/disable the bitmanip support by CVA6, could you add a config variable, as done in core/include/cv32a6_XXX_config_pkg.sv to configure it? The generation of the RTL dedicated to bitmanip should be conditioned by it (decode, alu,...).

Regards

M-Ijaz-10x · 2022-06-06T12:27:18Z

During synthesis of 32bits version, Error: ../..//core/csr_regfile.sv:574: Array index out of bounds instret[63:32], valid bounds are [31:0]. (ELAB-298)

Hello @JeanRochCoulon, the above error was due to the changes made in PR-847. Above commit proposed a workable solution for this error, but @spersvold will need to review the fix.

The remaining two errors have also been resolved in the latest commits.

In another hand, as we would be pleased to enable/disable the bitmanip support by CVA6, could you add a config variable, as done in core/include/cv32a6_XXX_config_pkg.sv to configure it? The generation of the RTL dedicated to bitmanip should be conditioned by it (decode, alu,...).

From the start, we are confining all the bitmanip RTL changes under the bitmanip parameter defined in ariane_pkg.sv as suggested by @zarubaf

ZenithalHourlyRate · 2022-06-06T13:04:35Z

core/alu.sv

+                ROL:          result_o = (fu_data_i.operand_a << fu_data_i.operand_b[5:0]) | (fu_data_i.operand_a >> (riscv::XLEN-fu_data_i.operand_b[5:0]));
+                ROLW:         result_o = {{riscv::XLEN-32{rolw[31]}}, rolw};
+                ROR, RORI:    result_o = (fu_data_i.operand_a >> fu_data_i.operand_b[5:0]) | (fu_data_i.operand_a << (riscv::XLEN-fu_data_i.operand_b[5:0]));
+                RORW, RORIW:  result_o = {{riscv::XLEN-32{rorw[31]}}, rorw};


#878 (comment)

Ahh, it seems that you did not resolve it. It turned out that I knew another technique but forget to add it in last review

It is observed that rol(x) = ror(reverse(w)), you can use ror(shift_op_a) to get rol(a), just as the current design uses srl to get sll

It is observed that rorw(x[31:0]) = ror({x[31:0],x[31:0]})[31:0]. If you still want to leave RORW and ROR as two separate datapaths, at least RORW and ROLW could be merged.

Thank you @ZenithalHourlyRate for your review, really appreciate it. I will make this last change in a separate follow-up PR. For now, I am keeping it in my notes. :)

spersvold

The change looks good to me. However, I noticed that "instret" will not work as intended when in 32-bit mode if you wrap it (because the incrementing logic in lines 333-349 is only dealing with the temporary variable "instret" which is xlen_t only, and then casting to instret_d after).

This should be fixed in a different commit though, so I approve this one.

JeanRochCoulon · 2022-06-07T13:12:21Z

Hello,
I get another eror compiling with VCS:
Error-[IRIPS] Illegal range in part select core-v-verif/core-v-cores/cva6/core/alu.sv, 191
The range of the part select is illegal: fu_data_i.operand_a[(riscv::XLEN - 33):0]
As you know, XLEN can be equal to 32... In that case, XLEN-33 is negative !
Have a nice day

JeanRochCoulon · 2022-06-23T09:37:20Z

I synthetized in 32 bits version, please find the error reported by dc_shell Synsopsys tool:

Error: ../..//core/alu.sv:287: Array index out of bounds fu_data_i[63:56], valid bounds are [31:0]. (ELAB-298)
*** Presto compilation terminated with 1 errors. ***
Information: Building the design 'alu'. (HDL-193)
Warning: Unable to resolve reference 'alu' in 'ex_stage_1'. (LINK-5)

Regards

zchamski · 2022-07-01T10:08:46Z

Hi @fatimasaleem, in order to make the validation of CVA6 synthesis smoother, we are implementing synthesis error/warning message extraction in the Thales public CI dashboard (https://riscv-ci.pages.thales-invia.fr/dashboard/dashboard_cva6.html).

Since this is still work in progress, here are the summaries of synthesis error/warning logs produced by our prototype filter on your latest push (20a181a). Please let @JeanRochCoulon, @yanicasa and myself (@zchamski) know if they are sufficient for you to work on your code.

Synthesis 32b (cv32a60x):
cva6-bitmanip-synth-errors-32b.g20a181a.txt

Synthesis 64b (cv64a6_imafdc_sv39):
cva6-bitmanip-synth-errors-64b.g20a181a.txt

As soon as the log extractor is stable (and incorporates the required usability adjustments if any) we will announce it in due way.

Co-authored-by: Florian Zaruba <[email protected]>

fatimasaleem · 2022-07-03T01:13:50Z

Hi @zchamski
I have made the required changes, can you please trigger the CI checks again? Thanks. cc @JeanRochCoulon

FYI: I have also run the latest arch-tests regression using the core-v-verif infrastructure with the PR-1254, it would be great if we could add these new arch-tests in the CI checks also.

zchamski · 2022-07-04T09:03:29Z

Hi @fatimasaleem, the synthesis in the CI looks good! BTW, the Thales public CI is triggered automatically on every Github push to either cva6 or core-v-verif, and you can check the CI results as follows:

Go to the Thales CI dashboard landing page at https://riscv-ci.pages.thales-invia.fr/dashboard/
Select the CVA6 dashboard:
Select the CI pipeline of interest and click on the PASS/FAIL status button:
Select a job of interest (typically 'ASIS Synthesis cv32a60x' or 'ASIC Synthesis cv64a6_imafdc_sv39') and click on its PASS/FAIL button:
This will display the log summaries of the given job. For synthesis, the summaries cover total area (in gate equivalents), area-by-category figures (gate equivs and percentage), area-by-package figures (again gate equivs and percentage), and finally, any error/warning messages.

Please let the usual suspects (@zchamski, @yanicasa, @JeanRochCoulon) know about your experience of using the Thales CI dashboard.

And to answer an almost certain question: no, there are no direct links to the inside of the dashboard, you have to click your way through...

fatimasaleem · 2022-07-04T09:42:29Z

Thank you @zchamski for the details. It really is very helpful.

@JeanRochCoulon Since the synthesis and regression run look green, can we merge this? or is there anything else that needs to be done/fixed?

Thanks & Regards,

JeanRochCoulon · 2022-07-06T14:07:40Z

Hello @fatimasaleem @M-Ijaz-10x @spersvold @zchamski
Good news, no regression has been detected ! I would like to thank you for this very good contribution. After merging this current PR, I will define bitmanip as a HW config parameter in config_pkg.sv. In cv64_imac_sv39, it will be enabled, and in cv32a60x config disabled. I will merge your PR as soon as the github action is pass. Cheers

JeanRochCoulon · 2022-07-06T14:45:43Z

In parallel, @ASintzoff will have a look to the arc-test suite PR. It would be nice to get it

M-Ijaz-10x requested a review from zarubaf as a code owner May 16, 2022 12:40

zarubaf requested changes May 23, 2022

View reviewed changes

zarubaf requested changes May 24, 2022

View reviewed changes

core/Flist.cv64a6_imafdc_sv39 Outdated Show resolved Hide resolved

core/alu.sv Outdated Show resolved Hide resolved

core/decoder.sv Outdated Show resolved Hide resolved

core/multiplier.sv Show resolved Hide resolved

zarubaf approved these changes May 24, 2022

View reviewed changes

M-Ijaz-10x closed this May 24, 2022

M-Ijaz-10x reopened this May 24, 2022

ZenithalHourlyRate reviewed May 28, 2022

View reviewed changes

ZenithalHourlyRate reviewed Jun 6, 2022

View reviewed changes

spersvold approved these changes Jun 6, 2022

View reviewed changes

fatimasaleem force-pushed the riscv-bitmanip-ext branch 2 times, most recently from 9e1c6b7 to 20a181a Compare June 28, 2022 09:45

M-Ijaz-10x added 9 commits July 3, 2022 00:44

Adding the updated Flist file

82a3a69

Adding the updated mult file

5d7d651

Adding the updated multiplier file

0fc5830

Adding the updated ariane_pkg file

c8d6690

Adding the updated alu file

1d9481a

Fixing enum width in ariane_pkg file

d73cda9

Adding updated RTL for clmul, clmulh, and clmulr instructions

5566c24

Adding the updated decoder file

d5f8aeb

Cleaning alu file for redundant rev8 RTL

939dd36

M-Ijaz-10x and others added 12 commits July 3, 2022 00:44

Adding updated RTL for clz, clzw, ctz, ctzw, cpop, cpopw instructions

fbf769b

Adding updated multiplier file

ddd3b27

Adding updated Makefile for adding BITMANIP macro definition

e1f2373

Adding the updated alu file

08dc1f3

Updated the ALU, MULT selection logic in the decoder file

975a6e6

Fixed the issue with the SRLW, SRAW selection logic

a566ba0

updated design files

98c1550

Update core/Flist.cv64a6_imafdc_sv39

723c656

Co-authored-by: Florian Zaruba <[email protected]>

Update core/multiplier.sv

f190d8e

Co-authored-by: Florian Zaruba <[email protected]>

minor code formatting

11af18b

optimized bitmanip design implementation

a49f55c

synthesis fix

e25192b

fatimasaleem force-pushed the riscv-bitmanip-ext branch from 20a181a to e25192b Compare July 3, 2022 01:07

JeanRochCoulon approved these changes Jul 6, 2022

View reviewed changes

JeanRochCoulon merged commit c23eed5 into openhwgroup:master Jul 6, 2022

zchamski mentioned this pull request Jul 11, 2022

Add preliminary support for Nexys Video board #350

Closed

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Adding Support for Zba, Zbb, Zbc and Zbs extensions to CVA6 #878

Adding Support for Zba, Zbb, Zbc and Zbs extensions to CVA6 #878

M-Ijaz-10x commented May 16, 2022

zarubaf left a comment

M-Ijaz-10x commented May 23, 2022

zarubaf left a comment

JeanRochCoulon commented May 24, 2022

M-Ijaz-10x commented May 24, 2022

zarubaf left a comment

M-Ijaz-10x commented May 24, 2022

M-Ijaz-10x commented Jun 1, 2022

JeanRochCoulon commented Jun 3, 2022

M-Ijaz-10x commented Jun 6, 2022

ZenithalHourlyRate Jun 6, 2022 •

edited

Loading

fatimasaleem Jul 3, 2022

spersvold left a comment

JeanRochCoulon commented Jun 7, 2022 •

edited

Loading

JeanRochCoulon commented Jun 23, 2022

zchamski commented Jul 1, 2022

fatimasaleem commented Jul 3, 2022 •

edited

Loading

zchamski commented Jul 4, 2022

fatimasaleem commented Jul 4, 2022

JeanRochCoulon commented Jul 6, 2022

JeanRochCoulon commented Jul 6, 2022

Adding Support for Zba, Zbb, Zbc and Zbs extensions to CVA6 #878

Adding Support for Zba, Zbb, Zbc and Zbs extensions to CVA6 #878

Conversation

M-Ijaz-10x commented May 16, 2022

Introduction

Implementation

Integration of bitmanip hardware with cva6

Verification

Assembly Tests

Core-v-verif environment

zarubaf left a comment

Choose a reason for hiding this comment

M-Ijaz-10x commented May 23, 2022

zarubaf left a comment

Choose a reason for hiding this comment

JeanRochCoulon commented May 24, 2022

M-Ijaz-10x commented May 24, 2022

zarubaf left a comment

Choose a reason for hiding this comment

M-Ijaz-10x commented May 24, 2022

M-Ijaz-10x commented Jun 1, 2022

JeanRochCoulon commented Jun 3, 2022

M-Ijaz-10x commented Jun 6, 2022

ZenithalHourlyRate Jun 6, 2022 • edited Loading

Choose a reason for hiding this comment

fatimasaleem Jul 3, 2022

Choose a reason for hiding this comment

spersvold left a comment

Choose a reason for hiding this comment

JeanRochCoulon commented Jun 7, 2022 • edited Loading

JeanRochCoulon commented Jun 23, 2022

zchamski commented Jul 1, 2022

fatimasaleem commented Jul 3, 2022 • edited Loading

zchamski commented Jul 4, 2022

fatimasaleem commented Jul 4, 2022

JeanRochCoulon commented Jul 6, 2022

JeanRochCoulon commented Jul 6, 2022

ZenithalHourlyRate Jun 6, 2022 •

edited

Loading

JeanRochCoulon commented Jun 7, 2022 •

edited

Loading

fatimasaleem commented Jul 3, 2022 •

edited

Loading