[jaopaulolc]

Motivation

TensileLite device library YAML files for gfx942 FreeSize configurations
contain parameter type mismatches (int stored where bool or float is
expected). These cause std::bad_cast exceptions at runtime when msgpack
deserialization encounters unexpected wire types.

This is part 1a of a 3-part series splitting #8623 into reviewable
chunks. This PR covers the aquavanjaram/gfx942/FreeSize/ subdirectory.

Technical Details

Bulk regex fixes applied to 100 YAML library logic files under
projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/aquavanjaram/gfx942/FreeSize/:

• int → bool: Activation, SourceSwap, TailloopInNll, TransposeA, TransposeB
  (e.g. Activation: 1 → Activation: true)
• int → float: GlobalReadPerMfma
  (e.g. GlobalReadPerMfma: 1 → GlobalReadPerMfma: 1.0)

No logic or behavior change; only corrects serialized types to match
TensileLite's schema expectations.

Test Plan

• Device library build for gfx942 passes type validation with zero mismatches
• CI gating builds for hipblaslt and hipsparselt pass
• Unit tests in test_validateParameterTypes.py confirm correct type detection

Test Result

• Local device library build completed with 0 type mismatch warnings
• Existing unit tests pass

Submission Checklist

• Look over the contributing guidelines at https://github.com/ROCm/ROCm/blob/develop/CONTRIBUTING.md#pull-requests.

Risk level

None — data-only change correcting serialized types to match schema; no logic change.

Associated ticket: N/A

PR Series

#	PR	Files	URL
1a	FreeSize gfx942 YAML fixes	100	#8680 👈
1b	GridBased small + 80cu/228cu YAML fixes	36	#8682
1c	GridBased large YAML files (>10MB)	26	#8683
2	gfx950/gfx1250/gfx11xx YAML + CustomKernels + hipsparselt	~120	#8678
3	Error promotion + test/config fixes	35	#8679

[jaopaulolc]

Closing in favour of #6609 which covers these fixes.

[codecov-commenter]

Codecov Report

✅ All modified and coverable lines are covered by tests.

❌ Your project status has failed because the head coverage (77.89%) is below the target coverage (80.00%). You can increase the head coverage or adjust the target coverage.

Additional details and impacted files

@@           Coverage Diff            @@
##           develop    #8680   +/-   ##
========================================
  Coverage    71.43%   71.43%           
========================================
  Files         2612     2612           
  Lines       406992   406992           
  Branches     60771    60771           
========================================
  Hits        290730   290730           
  Misses       94960    94960           
  Partials     21302    21302           

Flag	Coverage Δ		*Carryforward flag
TensileLite	76.83% <ø> (ø)		Carriedforward from fc34ca4
hipBLAS	90.81% <ø> (ø)		Carriedforward from fc34ca4
hipBLASLt	41.36% <ø> (ø)
hipCUB	82.68% <ø> (ø)		Carriedforward from fc34ca4
hipDNN	86.71% <ø> (ø)		Carriedforward from fc34ca4
hipFFT	50.79% <ø> (ø)		Carriedforward from fc34ca4
hipRAND	76.12% <ø> (ø)		Carriedforward from fc34ca4
hipSOLVER	69.18% <ø> (ø)		Carriedforward from fc34ca4
hipSPARSE	86.55% <ø> (ø)		Carriedforward from fc34ca4
rocBLAS	48.08% <ø> (ø)		Carriedforward from fc34ca4
rocFFT	47.22% <ø> (ø)		Carriedforward from fc34ca4
rocRAND	57.07% <ø> (ø)		Carriedforward from fc34ca4
rocSOLVER	77.89% <ø> (ø)		Carriedforward from fc34ca4
rocSPARSE	72.37% <ø> (ø)		Carriedforward from fc34ca4
rocThrust	91.34% <ø> (ø)		Carriedforward from fc34ca4

*This pull request uses carry forward flags. Click here to find out more.

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