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[tensilelite] Fix type mismatches in gfx950/gfx1250/gfx11xx device library YAML (2/3) - #8678
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…brary YAML Fix parameter type mismatches in gfx950, gfx1250, gfx1151, and gfx1201 logic files that cause std::bad_cast at runtime: - int -> bool: Activation, BufferStore, ExpandPointerSwap, LDSTrInst, MIArchVgpr, SourceSwap, StorePriorityOpt, TailloopInNll, Use64bShadowLimit, TransposeA, TransposeB - bool -> int: DirectToLds, DirectToLdsMetadata, SwapGlobalReadOrder, TransposeLDSMetadata, UsePLRPack - int -> float: GlobalReadPerMfma - float -> int: StaggerUStride
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Closing in favour of #6609 which covers these fixes. |
Codecov Report✅ All modified and coverable lines are covered by tests. ❌ Your project status has failed because the head coverage (77.89%) is below the target coverage (80.00%). You can increase the head coverage or adjust the target coverage. Additional details and impacted files@@ Coverage Diff @@
## develop #8678 +/- ##
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Coverage 71.43% 71.43%
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Files 2612 2612
Lines 406992 406992
Branches 60771 60771
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Hits 290730 290730
Misses 94960 94960
Partials 21302 21302
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Motivation
TensileLite device library YAML files for gfx950, gfx1250, gfx1151, and
gfx1201 configurations contain parameter type mismatches (int/bool/float
stored where a different type is expected). These cause
std::bad_castexceptions at runtime when msgpack deserialization encounters unexpected
wire types.
This is part 2 of a 3-part series splitting #8623 into reviewable chunks.
Technical Details
Bulk regex fixes applied to ~120 YAML library logic files and CustomKernels
assembly files (
.swith embedded YAML metadata) under:projects/hipblaslt/library/.../aquavanjaram/gfx950/projects/hipblaslt/library/.../aquavanjaram/gfx1250/projects/hipblaslt/library/.../aquavanjaram/gfx1151/projects/hipblaslt/library/.../aquavanjaram/gfx1201/projects/hipblaslt/tensilelite/Tensile/CustomKernels/*.sprojects/hipsparselt/library/.../aquavanjaram/gfx942/Conversions:
Activation,BufferStore,ExpandPointerSwap,LDSTrInst,MIArchVgpr,NoReject,PreloadKernArgs,SourceSwap,StorePriorityOpt,TailloopInNll,Use64bShadowLimit,TransposeA,TransposeBDirectToLds,DirectToLdsMetadata,SwapGlobalReadOrder,TransposeLDSMetadata,UsePLRPackGlobalReadPerMfmaStaggerUStrideNo logic or behavior change; only corrects serialized types to match
TensileLite's schema expectations.
Test Plan
test_validateParameterTypes.pyconfirm correct type detectionTest Result
Submission Checklist
Risk level
None — data-only change correcting serialized types to match schema; no logic change.
Associated ticket: N/A
PR Series