[mjkvaak-amd]

Purpose

When VLLM_ROCM_USE_AITER_FUSION_SHARED_EXPERTS is on, MoERunner concatenates the router gate and the shared-expert gate into a single [num_experts + num_shared, hidden] weight and computes the combined logits with a bare F.linear. The un-fused VLLM_ROCM_USE_AITER_FUSION_SHARED_EXPERTS=0 branch immediately below it calls self.gate(hidden_states), a ReplicatedLinear whose UnquantizedLinearMethod.apply goes through dispatch_unquantized_gemm().

The problem is that FSE silently replaced ROCm's skinny-GEMM kernels with Tensile Cijk_* kernels firing once per MoE layer
per decode step. Those kernels cost 110.6 ms per 100 decode steps where the skinny path does the same GEMM in 55.6 ms, a nearly 2x regression on this GEMM.

This PR routes the fused path through dispatch_unquantized_gemm() as well.

• On ROCm that reaches rocm_unquantized_gemm, matching the un-fused path;
• On every other platform dispatch_unquantized_gemm() returns F.linear, so the change is a no-op there.

Beyond the immediate win, this also puts the fused gate back onto the path that can reach AITER's tuned GEMM at all. F.linear goes straight to rocBLAS and never consults AITER for tuned kernels. After this change the GEMMs flow through rocm_unquantized_gemm_impl into aiter.tuned_gemm.mm, and any tuned configuration AITER ships for this shape is picked up automatically with no further vLLM change.

Test Plan

Models

• amd/Qwen3.8-2.4T-A95B-Quark-MXFP4 -> Quark-MXFP4: publicly available, for baseline
• amd/Qwen3.8-2.4T-A95B-MoE-MXFP4 -> MoE-MXFP4: custom checkpoint enabling FP4-quantized fused shared experts

All runs on MI355X (gfx950), TP8, --kv-cache-dtype fp8, AITER attention, --ignore-eos, identical seeds on both arms; the arms differ only by this patch.

Kernel-level. PyTorch profiler traces over a decode-only window, comparing per-kernel time before and after.

Serving throughput and latency.

ISL	OSL	Max concurrency	Prompts
1024	1024	4	32
1024	1024	8	64
1024	1024	16	96
1024	1024	32	128
1024	1024	128	384

Accuracy. GSM8K, 5-shot, three arms -- Quark-MXFP4 with FSE off, MoE-MXFP4 with FSE off, MoE-MXFP4 with FSE on -- to keep the checkpoint change separate from the fused-shared-experts change.

Test Result

Kernels

Decode-only trace at conc=4; ms per 100 decode steps:

Arm	Total	wvSplitK	Tensile Cijk_*
Fused shared experts off	1807.5	330.4	0.0
Fused shared experts on, before this PR	1419.8	275.2	110.6
Fused shared experts on, with this PR	1368.9	330.8	0.0

The Cijk_* kernels disappear and total wvSplitK time returns to the un-fused level (330.8 against 330.4), which confirms the fused 513-wide gate is no more expensive than the 512-wide router gate it replaces. Net recovery is about 51 ms per 100 decode steps.

Serving benchmarks

Median of three runs per case for the patched arm, one run per case for the baseline. Each cell is before → after (change); higher is better for throughput, lower for latency.

ISL	OSL	Conc	Prompts	Output tok/s	Mean TTFT (ms)	Mean TPOT (ms)	Mean E2EL (ms)
1024	1024	4	32	279.6 → 289.4 (+3.5%)	177.1 → 179.1 (+1.1%)	13.78 → 13.29 (-3.5%)	13,445.7 → 12,988.4 (-3.4%)
1024	1024	8	64	414.7 → 415.6 (+0.2%)	214.4 → 215.3 (+0.4%)	17.74 → 17.74 (-0.0%)	16,860.0 → 16,860.3 (+0.0%)
1024	1024	16	96	687.6 → 687.5 (-0.0%)	284.0 → 283.5 (-0.2%)	21.02 → 21.06 (+0.2%)	22,840.0 → 22,894.9 (+0.2%)
1024	1024	32	128	976.1 → 972.5 (-0.4%)	411.5 → 445.7 (+8.3%)	28.17 → 28.40 (+0.8%)	29,632.2 → 29,870.6 (+0.8%)
1024	1024	128	384	2,178.8 → 2,165.4 (-0.6%)	1,298.6 → 1,295.7 (-0.2%)	49.72 → 50.25 (+1.1%)	51,305.5 → 51,752.2 (+0.9%)

Geometric mean output throughput over the five cases: +0.5%.

rocm_unquantized_gemm_impl only selects the wvSplitK skinny kernels when the token count is at most 5. At concurrency 4 the decode batch stays inside that window, which is where the +3.5% comes from. Above it, the call falls through to aiter.tuned_gemm.mm, whose tuned table has no entry for the 513-wide fused gate, so the lookup misses and AITER circles back to its default torch solution -- the same rocBLAS kernel the previous F.linear used. Performance above that boundary is therefore unchanged by construction, and the flat rows are the expected result rather than a regression.

That gap is on the ROCm/AITER side, not in vLLM. Tuning the shape offline (N=513, K=8192, bf16, on gfx950) shows the fallback is leaving performance on the table at every batch size tested, at no cost in accuracy (error ratio 0.0 for every selected kernel):

Tokens	rocBLAS fallback	Best available (hipBLASLt)	Speedup
8	12.10 µs	8.85 µs	1.37x
16	11.63 µs	8.75 µs	1.33x
64	12.53 µs	11.08 µs	1.13x
256	15.36 µs	14.28 µs	1.07x
1024	28.86 µs	23.25 µs	1.24x
8192	108.18 µs	89.66 µs	1.21x

Closing that gap belongs in AITER, as tuned configurations for the fused gate width and, potentially, relaxed shape constraints. This PR is the prerequisite for any of it reaching the fused path: as long as the gate went through F.linear, AITER was never consulted for this GEMM at all. Once those configurations land, the fused gate picks them up with no further vLLM changes.

GSM8K

5-shot, 1319 problems, lm_eval with tensor_parallel_size=8, max_gen_toks=2048, seed 4321.

Arm	flexible-extract	strict-match
Quark-MXFP4, fused shared experts off	0.9318 ± 0.0069	0.9333 ± 0.0069
MoE-MXFP4, fused shared experts off	0.9310 ± 0.0070	0.9318 ± 0.0069
MoE-MXFP4, fused shared experts on	0.9280 ± 0.0071	0.9280 ± 0.0071
MoE-MXFP4, fused shared experts on, with this PR	0.9227 ± 0.0074	0.9219 ± 0.0074

All four arms are statistically indistinguishable; the widest gap, between the Quark-MXFP4 reference and this PR, is 1.1 standard errors of the difference. The second arm isolates the checkpoint change (shared expert pre-quantized to MXFP4) from fusion itself, so the third is attributable to fusion alone, and the fourth to this patch alone.

---

Co-authored by: Cursor

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[amd-mghanimi]

If I understand correctly from the explanation, it is better to replace instances of F.linear or torch.nn.functional.linear calls that run with no quantization with this wrapper dispatch_unquantized_gemm().
because dispatch_unquantized_gemm can choose the right device path?

here:

vllm/vllm/model_executor/layers/utils.py

Lines 561 to 569 in 3140531

	def dispatch_unquantized_gemm(
	linear_backend: str = "auto",
	) -> Callable[..., torch.Tensor]:
	if current_platform.is_rocm():
	return rocm_unquantized_gemm
	elif current_platform.is_cpu():
	return cpu_unquantized_gemm
	elif not current_platform.is_cuda():
	return default_unquantized_gemm

for example should we also replace the fallback path here?

vllm/vllm/model_executor/layers/fused_moe/router/gate_linear.py

Lines 207 to 229 in 3140531

	def fp32_router_gemm_dispatch_impl(
	x: torch.Tensor,
	weight: torch.Tensor,
	allow_bf16x3_router_gemm: bool,
	) -> torch.Tensor:
	"""
	Dynamically run fp32 specialized gemm if num_tokens <= FP32_MAX_TOKENS,
	otherwise optionally run the experimental BF16x3 kernel for medium/large
	SM100 router batches, then fall back to F.linear.
	This must be wrapped in a custom op because our torch.compile integration
	does not support runtime dispatching on num_tokens.
	"""
	if x.shape[0] <= _FP32_ROUTER_GEMM_MAX_TOKENS:
	return ops.fp32_router_gemm(x, weight)
	if allow_bf16x3_router_gemm and x.dtype == torch.bfloat16:
	from vllm.model_executor.layers.fused_moe.router.bf16x3_router_gemm_cutedsl import ( # noqa: E501
	bf16x3_router_gemm,
	)
	return bf16x3_router_gemm(x, weight)
	return torch.nn.functional.linear(x.float(), weight)

[github-actions]

✅ @mjkvaak-amd, CI is now available for this PR.

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[dllehr-amd]

Looks straightforward Thanks @mjkvaak-amd

[mjkvaak-amd]

/ci run

[github-actions]

✅ Triggered Buildkite CI #89991 for commit d8eae36e47b1.

[tjtanaa]

/ci run

[github-actions]

✅ Triggered Buildkite CI #90245 for commit 342221b44037.