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Issues: chipsalliance/verible

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Issues list

Fail to build with GCC 15 build system matters pertaining to building Verible
#2400 opened May 2, 2025 by IEncinas10
goto definition crash with large code base language-server Language server related issues
#2395 opened Apr 22, 2025 by wpeet
Debug problems encountered
#2392 opened Apr 16, 2025 by liuyd-own
Module instances counted as signal names style-linter Verilog style-linter issues
#2388 opened Apr 9, 2025 by Khrig
parameter-name-style regex without OR enhancement New feature or request style-linter Verilog style-linter issues
#2387 opened Apr 8, 2025 by Khrig
Error when missing module language-server Language server related issues
#2385 opened Apr 7, 2025 by qarlosalberto
Quiet mode language-server Language server related issues
#2377 opened Mar 30, 2025 by qarlosalberto
Disable linter language-server Language server related issues
#2376 opened Mar 29, 2025 by qarlosalberto
wrong formatting of consecutive directives formatter Verilog code formatter issues
#2369 opened Mar 24, 2025 by keesj
max field identifier in binsof is recognized as wrong syntax rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2367 opened Mar 22, 2025 by ButterSus
Veribles formatter fails to parse input formatter Verilog code formatter issues
#2364 opened Mar 18, 2025 by joaovam
Formatter Features Request
#2363 opened Mar 13, 2025 by Remillard
Verible's formatter fails to lex/parse input formatter Verilog code formatter issues
#2359 opened Feb 20, 2025 by joaovam
let construct formatting formatter Verilog code formatter issues
#2348 opened Jan 31, 2025 by Sladkoeshechka
Interface class formatting formatter Verilog code formatter issues
#2347 opened Jan 31, 2025 by Sladkoeshechka
Error lex/parsing-ing formatted output. formatter Verilog code formatter issues
#2346 opened Jan 31, 2025 by Sladkoeshechka
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