Formatter fails to converge due to attribute for port and comment (with a few spaces) after second port definition

[david-sawatzke]

Test case

module foo (
    (* something *) input  logic bar,
                    input  logic barfoo            // comment

);
endmodule

with verible-verilog-format foo.sv

Actual output

foo.sv: Re-formatted text does not match formatted text; formatting failed to converge!  Please file a bug.
========== Original: --lines: ==========
module foo (
    (* something *) input  logic bar,
                    input  logic barfoo            // comment

);
endmodule
============== Formatted: ==============
module foo (
    (* something *) input logic bar,
                    input logic barfoo  // comment

);
endmodule
============= Re-formatted: ============
module foo (
    (* something *) input logic bar,
    input logic barfoo  // comment

);
endmodule
============== Diffs are: ==============
 module foo (
     (* something *) input logic bar,
-                    input logic barfoo  // comment
+    input logic barfoo  // comment
 
 );
 endmodule
; problematic formatter output is
module foo (
    (* something *) input logic bar,
                    input logic barfoo  // comment

);
endmodule
<<EOF>>

Expected or suggested output
When manually removing the spaces before the comment, the formatter does work as the first formatting step is skipped:

module foo (
    (* something *) input  logic bar,
                    input  logic barfoo // comment

);
endmodule

Result:

module foo (
    (* something *) input logic bar,
    input logic barfoo  // comment

);
endmodule