prevent merging single-line statements without begin/end onto the same line of if/else

[Liuliuliu7]

Test case

// Input to the formatter, preferably a reduced test case.
        if (test) 
          test_reg <= 1'b1;
        else
          test_reg <= 1'b0;

Include any options or configuration used.
--indentation_spaces=2
--assignment_statement_alignment=align
--case_items_alignment=align --named_port_alignment=align
--port_declarations_alignment=align
--module_net_variable_alignment=align
--wrap_end_else_clauses --line_break_penalty=0
--compact_indexing_and_selections=false
--column_limit=80

Actual output

// This doesn't look right.
        if (test) test_reg <= 1'b1;
        else test_reg <= 1'b0;

Expected or suggested output

// This result would look better from the formatter.
        if (test) 
          test_reg <= 1'b1;
        else
          test_reg <= 1'b0;

I don’t want single-line statements without begin/end to be forcibly merged onto the same line as if/else. Is there an existing option in verible-verilog-format ?