verible-verilog-format inserting spaces around *nix path separators, resulting in compile errors.

[AIS-L]

Test case

// Input to the formatter, preferably a reduced test case.
`PROJECT_INCLUDE(`PATH_MY_MODULE/src/config_class.sv)

Include any options or configuration used.

Actual output

// This doesn't look right.
`PROJECT_INCLUDE(`PATH_MY_MODULE / src / config_class.sv)

Include any possible diagnostic messages from the formatter.

Expected or suggested output
PROJECT_INCLUDE( PATH_MY_MODULE/src/config_class.sv )

// This result would look better from the formatter.

Citations to published style guides would help.