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Pull requests: chipsalliance/verible
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Adding regex configuration to the parameter-name-style rule
#2213
opened Jul 9, 2024 by
sconwayaus
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Added regex configuration to the interface name rule
#2211
opened Jul 9, 2024 by
sconwayaus
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Add a regex configration for the signal name style rule
#2204
opened Jun 17, 2024 by
sconwayaus
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Avoid comparison against nullptr, instead use it as boolean identity.
#2168
opened Apr 20, 2024 by
hzeller
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linter: make constraint-name-style configurable
#2017
opened Sep 23, 2023 by
IEncinas10
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1 task done
[LSP] Initial support for textDocument/hover request
#1922
opened May 16, 2023 by
glatosinski
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4 of 7 tasks
Provide autofixes for always_ff_non_blocking_rule
#1912
opened May 8, 2023 by
IEncinas10
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2 of 3 tasks
Format preprocessed token stream in multiple passes
#1898
opened Apr 28, 2023 by
kbieganski
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[VeriblePreProcessor][5]: White-spaces support in "VerilogPreprocess" class.
#1376
opened Aug 4, 2022 by
karimtera
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