[Bugfix][Quantization][XPU] Fix GPTQ MoE loading under moe_wna16

[afierka-intel]

Blocks afierka-intel#6 — this PR fixes the checkpoint-loading bugs that PR needs to reproduce its end-to-end results. This PR is independent and complete on its own.

Summary

Three independently-required fixes to load a real GPTQ MoE checkpoint through --quantization moe_wna16. Found running Qwen/Qwen1.5-MoE-A2.7B-Chat-GPTQ-Int4.

#	Fix	Failure without it
1	moe_wna16 added to XPUPlatform.supported_quantization	ValidationError: ... not supported in xpu
2	packed_modules_mapping propagated to the linear delegate in moe_wna16.py	fused layers built unquantized; qweight/qzeros/scales have nowhere to load
3	XPU oracle guard + TRITON fallback in int_wna16.py	fix 1 alone lets a MoeWNA16 checkpoint reach XPU's native kernel, which contracts on a different weight layout and would mis-shape the tensor rather than reject it

Fix 1 — nothing in MoeWNA16Config is CUDA-specific for GPTQ checkpoints; the allowlist simply never listed it. No-op on CUDA (CudaPlatform defines no allowlist at all).

Fix 2 — the delegate is rebuilt from the raw HF dict via AutoGPTQConfig.from_config(), which never sees packed_modules_mapping (attached to the parent config afterwards by the loader). Without it, gate_up_proj/qkv_proj match nothing in modules_in_block_to_quantize, so the layer registers only a plain weight. Now cached (MoeWNA16Config.linear_quant_config) so the loader's maybe_update_config/apply_vllm_mapper hooks — which MoeWNA16Config previously didn't forward at all — reach the same delegate instance get_quant_method() consults.

Overlaps with #35865 (same gap), but that PR is stale (2026-05-23) and targets classes that no longer exist on current main. This is the minimal equivalent; happy to defer if vllm-project#35865 is revived.

Fix 3 — the guard rejects the MoeWNA16 layout on XPU's native kernel explicitly (_backend_incompatibility_reason), naming --moe-backend triton as the fix. That alone left --moe-backend auto (the common case) dead-ending in a bare NotImplementedError, since TRITON was never an auto candidate on XPU. _get_priority_backends() now offers it as a fallback — no performance tradeoff, since TRITON is the only backend this layout can ever run on.

Test plan

10 test functions / 15 parametrized cases in tests/quantization/test_moe_wna16.py, one per fix plus shared cases. Measured on real Intel B70: baseline (pristine main) 4 failed, 11 passed → patched 15 passed. Each fix also reverted individually on hardware, reproducing the failure in the table above.

End-to-end on both platforms, with --moe-backend auto (not the explicit override — the fix under test is that auto must resolve correctly on its own). Both select and execute the same kernel (Using TritonWNA16Experts in the startup log, fused_moe_kernel_gptq_awq JIT-compiling at inference) and produce the identical generation for the same prompt — a strong signal for a weight-loading change: same weights, same places, same kernel, on both platforms.

ruff check + ruff format --check clean. None of the three fixes execute during inference — fix 1 is a one-time allowlist check, fix 2's delegate build is now cached rather than rebuilt, fix 3 adds one candidate to a list consulted once per model construction — so no serving-path benchmark is included; there is no mechanism by which these changes could show up in one.

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AI assistance was used (Claude Code) for implementation and testing; every changed line was reviewed and all tests above were run personally on Intel B70 and NVIDIA B200 hardware.

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[afierka-intel]

Restructured after review. This PR is now the minimal GPTQ-MoE loading fix: the XPU allowlist entry + packed_modules_mapping propagation (2 files, +12/-6).

Two fixes were removed:

• RoutedExperts.load_weights (was fix 4) — dropped, superseded upstream. vllm-project/vllm#50937 (70456e5e6f, merged Aug 7) landed the same guard in the same lines and shipped its own test. I checked whether my break-instead-of-continue variant was a real difference: it is not. For a fused tensor with no registered param, upstream's continue visits one extra mapping entry that resolves to the same param name, still None, so it skips again — no double-load, no observable divergence. Nothing left to contribute.
• linear.py weight-loader refactor (was fix 3) — split to #13. It touches every model's load path and deserves separate review, and it is demonstrably not what unblocks this model.

Also: title dropped "and dispatch" (the diff contains no dispatch change), and rebased onto current main (bd6536071c, was 118+ commits behind).

Evidence re-run against current main, since the rebase invalidated the old numbers. The PR body previously claimed "4 failed on pristine main" — measured on the stale base. On current main it is 3, on both platforms:

platform	pristine main	patched
H200 NVL (CI image @ bd6536071c)	3 failed, 2 passed	5 passed
Intel B70 (XPU CI image @ b22afe45ac)	3 failed, 2 passed	5 passed

The vanished 4th failure was exactly fix 4's w2_bias case. Those numbers now live in #13, which owns that test file.

[afierka-intel]

Superseded by vllm-project/vllm#52651. Closing the fork PR.