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Hi @tgmerritt, the pre-commit checks have failed. Please run: uv pip install pre-commit>=4.5.1
pre-commit install
pre-commit run --all-filesThen, commit the changes and push to your branch. For future commits, Tip Is
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Pre-commit checks ran locally against all changed files and passed: The CI |
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Status update for reviewers:
Could a maintainer add |
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I don't think it will compile with our current cutlass version? |
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@Harry-Chen You're reading the pin correctly — To be concrete that it's only the pin and not the code — from a full from-source build today (2026-06-09), vLLM v0.22.1 base + this PR's changes, CUTLASS 4.5.1 with the #3280 collective applied via Build completed cleanly and that image is serving a Gemma-4 26B MoE deployment on GB10 (SM121) in production today, CUTLASS grouped path active (+7.3% short-sequence throughput vs. the fallback, per the description). If reviewers would rather not wait on the CUTLASS pin: I can compile-gate the SM120 grouped source (and key the Python gate to the same build flag) so this merges green against v4.4.2 and lights up automatically when the pin advances past #3280. Happy to push that variant. |
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A quick production note while this thread is active: with our v022-sm121 build running on DGX Spark (SM121), the runtime logs confirm This suggests #43814 covers the standard FP8 grouped MoE path — and we did confirm a +7.3% short-sequence throughput uplift on the FP8-Dynamic (non-MXFP8) checkpoint after applying the patch. For MXFP8 W8A8, the MoE path routes to MARLIN regardless, which is a separate kernel question being tracked in flashinfer#3463 / flashinfer#3549. On the CUTLASS version gate: the compile-gated variant offer from the previous comment stands. Happy to implement a CMake probe + |
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Cross-project corroboration that may help de-risk this for reviewers: the sibling SM120 grouped collective just shipped in sglang — sgl-project/sglang#28125 adds the SM120/SM121 dispatch for It's a different scaling epilogue from this PR (blockwise Happy to validate this PR's exact path on the RTX PRO 6000 too once the CUTLASS pin (or a |
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This pull request has merge conflicts that must be resolved before it can be |
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…onsumer Blackwell Fixes two bugs that silently disabled the CUTLASS FP8 grouped GEMM path for all SM_120/SM_121 hardware (RTX 5090/5080/5070, DGX Spark GB10): 1. Python gate (`vllm/_custom_ops.py`): `cuda_device_capability >= 110` evaluated to True for SM121 (121 >= 110), returning False and routing every MoE dispatch to the Triton fallback. Changed to `>= 130` to correctly allow SM12x. 2. Missing SM120 kernel (`grouped_mm_c3x_sm120.cu`): Added the SM120 analog of `grouped_mm_c3x_sm100.cu`. Uses `KernelPtrArrayTmaWarpSpecializedCooperativeSm120<2>` with tile shape 128x128x128 and ClusterShape 1x1x1 (no programmatic multicast on consumer Blackwell). Dispatch added to `scaled_mm_entry.cu` for SM version 120-129. The SM120 CUTLASS collective required to instantiate this kernel (`MainloopSm120ArrayTmaWarpSpecialized`) is being contributed upstream via NVIDIA/cutlass#3280 (currently in review). vLLM builds should pick it up once CUTLASS 4.6 or a pinned revision containing that PR is used. Validated on real SM_121 hardware (NVIDIA DGX Spark, GB10, 128 GB LPDDR5X) with `RedHatAI/gemma-4-26B-A4B-it-FP8-Dynamic` (Gemma 4 MoE, FP8-Dynamic). Short-sequence decode throughput improved ~7% (76.3 → 81.9 tok/s) vs the Triton fallback. Kernel produces correct outputs confirmed against baseline. Closes vllm-project#43507 Co-authored-by: Claude <noreply@anthropic.com> Signed-off-by: Tyler Merritt <tgmerritt@gmail.com>
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Rebased onto current `main` (post-v0.23.0) — applied cleanly, no conflicts. Pinging @Harry-Chen and @mgoin given your recent work on the SM12x / quantization area:
v0.23.1rc0 just appeared — would be great to get this in before the rc hardens. The change is small (one integer constant + one new ~108-line |
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I think you can continue your work after #47442 is merged. |
Port five upstream consumer-Blackwell capabilities so non-DSv4 workloads can serve on GB10 (sm_121, same family as RTX 5090 / RTX PRO 6000 sm_120): 1. TRTLLM fp8 MoE device gate -> SM_12x (upstream vllm-project#43911). 2. OAI Triton MoE capability window -> (9,0) <= cap < (13,0), covering SM120/SM121; kernels are pure Triton JIT with no sm90/sm10x-only instructions (upstream vllm-project#41028). 3. CUTLASS grouped GEMM w8a8 for SM120 (upstream vllm-project#43814): new grouped_mm_c3x_sm120.cu in FP4_SM120_SRCS, ENABLE_CUTLASS_MOE_SM120 dispatch + group_gemm_supported range in entry and _custom_ops.py. The CMake flag already existed (fork); this wires the kernel it promised. 4. NVFP4 grouped MoE pingpong schedule at per-expert M >= 512 (upstream vllm-project#46481): template<bool UsePingpong> on the sm120 entry; the fork's batch-invariance static_assert now pins each instantiation (cooperative stays the default/batch-invariant path). 5. CUTLASS MXFP4 W4A4 MoE on SM12x (upstream vllm-project#51158): mxfp4 kernels join FP4_SM120_SRCS; kernel/test files byte-match the PR head. Deferred (tracked on #48): vllm-project#46329 NVFP4 KV-cache enablement — fork files diverge 300-700 lines (nvfp4_ds_mla ABI, envs, flashinfer backend); needs a hand-merge plus GB10 GPU validation. vllm-project#50288's V-scale-swizzle fix is already contained in 46329's kernel. Verified: py files compile; pre-commit clean (clang-format applied); test_mxfp4_moe skips in this venv (no GPU/triton_kernels) — GPU validation rides the next Spark image build. Co-authored-by: OMP Agent <noreply@omp.local> Signed-off-by: Naadir Jeewa <naadir@randomvariable.co.uk>
Port five upstream consumer-Blackwell capabilities so non-DSv4 workloads can serve on GB10 (sm_121, same family as RTX 5090 / RTX PRO 6000 sm_120): 1. TRTLLM fp8 MoE device gate -> SM_12x (upstream vllm-project#43911). 2. OAI Triton MoE capability window -> (9,0) <= cap < (13,0), covering SM120/SM121; kernels are pure Triton JIT with no sm90/sm10x-only instructions (upstream vllm-project#41028). 3. CUTLASS grouped GEMM w8a8 for SM120 (upstream vllm-project#43814): new grouped_mm_c3x_sm120.cu in FP4_SM120_SRCS, ENABLE_CUTLASS_MOE_SM120 dispatch + group_gemm_supported range in entry and _custom_ops.py. The CMake flag already existed (fork); this wires the kernel it promised. 4. NVFP4 grouped MoE pingpong schedule at per-expert M >= 512 (upstream vllm-project#46481): template<bool UsePingpong> on the sm120 entry; the fork's batch-invariance static_assert now pins each instantiation (cooperative stays the default/batch-invariant path). 5. CUTLASS MXFP4 W4A4 MoE on SM12x (upstream vllm-project#51158): mxfp4 kernels join FP4_SM120_SRCS; kernel/test files byte-match the PR head. Deferred (tracked on #48): vllm-project#46329 NVFP4 KV-cache enablement — fork files diverge 300-700 lines (nvfp4_ds_mla ABI, envs, flashinfer backend); needs a hand-merge plus GB10 GPU validation. vllm-project#50288's V-scale-swizzle fix is already contained in 46329's kernel. Verified: py files compile; pre-commit clean (clang-format applied); test_mxfp4_moe skips in this venv (no GPU/triton_kernels) — GPU validation rides the next Spark image build. Co-authored-by: OMP Agent <noreply@omp.local> Signed-off-by: Naadir Jeewa <naadir@randomvariable.co.uk>
Port five upstream consumer-Blackwell capabilities so non-DSv4 workloads can serve on GB10 (sm_121, same family as RTX 5090 / RTX PRO 6000 sm_120): 1. TRTLLM fp8 MoE device gate -> SM_12x (upstream vllm-project#43911). 2. OAI Triton MoE capability window -> (9,0) <= cap < (13,0), covering SM120/SM121; kernels are pure Triton JIT with no sm90/sm10x-only instructions (upstream vllm-project#41028). 3. CUTLASS grouped GEMM w8a8 for SM120 (upstream vllm-project#43814): new grouped_mm_c3x_sm120.cu in FP4_SM120_SRCS, ENABLE_CUTLASS_MOE_SM120 dispatch + group_gemm_supported range in entry and _custom_ops.py. The CMake flag already existed (fork); this wires the kernel it promised. 4. NVFP4 grouped MoE pingpong schedule at per-expert M >= 512 (upstream vllm-project#46481): template<bool UsePingpong> on the sm120 entry; the fork's batch-invariance static_assert now pins each instantiation (cooperative stays the default/batch-invariant path). 5. CUTLASS MXFP4 W4A4 MoE on SM12x (upstream vllm-project#51158): mxfp4 kernels join FP4_SM120_SRCS; kernel/test files byte-match the PR head. Deferred (tracked on #48): vllm-project#46329 NVFP4 KV-cache enablement — fork files diverge 300-700 lines (nvfp4_ds_mla ABI, envs, flashinfer backend); needs a hand-merge plus GB10 GPU validation. vllm-project#50288's V-scale-swizzle fix is already contained in 46329's kernel. Verified: py files compile; pre-commit clean (clang-format applied); test_mxfp4_moe skips in this venv (no GPU/triton_kernels) — GPU validation rides the next Spark image build. Co-authored-by: OMP Agent <noreply@omp.local> Signed-off-by: Naadir Jeewa <naadir@randomvariable.co.uk>
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Rebase and blocker status, since this has been quiet since July. The rebase is a no-op. I applied this commit onto I think the named blocker was the wrong one. @Harry-Chen suggested continuing after #47442, and #47442 merged on 2026-07-16. But #47442 bumps # CMakeLists.txt:486
set(CUTLASS_REVISION "v4.4.2")
# CMakeLists.txt:500-504
FetchContent_Declare(cutlass GIT_TAG ${CUTLASS_REVISION})
Why that matters here specifically. This PR's description says it needs
If that reading is right, the actual prerequisite is a Happy to be wrong about this. It is two lines of CMakeLists and easy to check. Offer: I have two DGX Sparks (GB10, sm_121) and can validate a One caution for anyone reading this thread as "SM12x FP8 is nearly there": #43911 is a separate matter. @mlobree reproduced on GB10 that widening the AI assistance: used Claude for the repository archaeology and to check the tagged CUTLASS trees. The rebase, the CMakeLists reading, and the tag comparison are reproducible from the commands above; I have not built on hardware yet. |
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Testing cutlass version bump in #54190. If it does not break other things, we can surely have a newer cutlass. |
Port five upstream consumer-Blackwell capabilities so non-DSv4 workloads can serve on GB10 (sm_121, same family as RTX 5090 / RTX PRO 6000 sm_120): 1. TRTLLM fp8 MoE device gate -> SM_12x (upstream vllm-project#43911). 2. OAI Triton MoE capability window -> (9,0) <= cap < (13,0), covering SM120/SM121; kernels are pure Triton JIT with no sm90/sm10x-only instructions (upstream vllm-project#41028). 3. CUTLASS grouped GEMM w8a8 for SM120 (upstream vllm-project#43814): new grouped_mm_c3x_sm120.cu in FP4_SM120_SRCS, ENABLE_CUTLASS_MOE_SM120 dispatch + group_gemm_supported range in entry and _custom_ops.py. The CMake flag already existed (fork); this wires the kernel it promised. 4. NVFP4 grouped MoE pingpong schedule at per-expert M >= 512 (upstream vllm-project#46481): template<bool UsePingpong> on the sm120 entry; the fork's batch-invariance static_assert now pins each instantiation (cooperative stays the default/batch-invariant path). 5. CUTLASS MXFP4 W4A4 MoE on SM12x (upstream vllm-project#51158): mxfp4 kernels join FP4_SM120_SRCS; kernel/test files byte-match the PR head. Deferred (tracked on #48): vllm-project#46329 NVFP4 KV-cache enablement — fork files diverge 300-700 lines (nvfp4_ds_mla ABI, envs, flashinfer backend); needs a hand-merge plus GB10 GPU validation. vllm-project#50288's V-scale-swizzle fix is already contained in 46329's kernel. Verified: py files compile; pre-commit clean (clang-format applied); test_mxfp4_moe skips in this venv (no GPU/triton_kernels) — GPU validation rides the next Spark image build. Co-authored-by: OMP Agent <noreply@omp.local> Signed-off-by: Naadir Jeewa <naadir@randomvariable.co.uk>
Port five upstream consumer-Blackwell capabilities so non-DSv4 workloads can serve on GB10 (sm_121, same family as RTX 5090 / RTX PRO 6000 sm_120): 1. TRTLLM fp8 MoE device gate -> SM_12x (upstream vllm-project#43911). 2. OAI Triton MoE capability window -> (9,0) <= cap < (13,0), covering SM120/SM121; kernels are pure Triton JIT with no sm90/sm10x-only instructions (upstream vllm-project#41028). 3. CUTLASS grouped GEMM w8a8 for SM120 (upstream vllm-project#43814): new grouped_mm_c3x_sm120.cu in FP4_SM120_SRCS, ENABLE_CUTLASS_MOE_SM120 dispatch + group_gemm_supported range in entry and _custom_ops.py. The CMake flag already existed (fork); this wires the kernel it promised. 4. NVFP4 grouped MoE pingpong schedule at per-expert M >= 512 (upstream vllm-project#46481): template<bool UsePingpong> on the sm120 entry; the fork's batch-invariance static_assert now pins each instantiation (cooperative stays the default/batch-invariant path). 5. CUTLASS MXFP4 W4A4 MoE on SM12x (upstream vllm-project#51158): mxfp4 kernels join FP4_SM120_SRCS; kernel/test files byte-match the PR head. Deferred (tracked on #48): vllm-project#46329 NVFP4 KV-cache enablement — fork files diverge 300-700 lines (nvfp4_ds_mla ABI, envs, flashinfer backend); needs a hand-merge plus GB10 GPU validation. vllm-project#50288's V-scale-swizzle fix is already contained in 46329's kernel. Verified: py files compile; pre-commit clean (clang-format applied); test_mxfp4_moe skips in this venv (no GPU/triton_kernels) — GPU validation rides the next Spark image build. Co-authored-by: OMP Agent <noreply@omp.local> Signed-off-by: Naadir Jeewa <naadir@randomvariable.co.uk>
4 participants
Summary
Fixes two bugs that silently disabled the CUTLASS FP8 grouped GEMM path for all SM_120/SM_121 hardware (RTX 5090/5080/5070, DGX Spark GB10), causing every MoE expert dispatch to fall back to the Triton backend.
Fixes #43507.
What changed
Bug 1 — Python gate (
vllm/_custom_ops.py)```python
Before (wrong):
if cuda_device_capability < 90 or cuda_device_capability >= 110:
return False
After (correct):
if cuda_device_capability < 90 or cuda_device_capability >= 130:
return False
```
`cuda_device_capability` is an integer: `121 >= 110` is `True`, so this gate always returned `False` for SM121, routing every call through Triton. `>= 130` is correct — it reserves the exit clause for genuinely unsupported future architectures beyond SM12x.
Bug 2 — Missing SM120 grouped GEMM kernel
Added `csrc/libtorch_stable/quantization/w8a8/cutlass/moe/grouped_mm_c3x_sm120.cu`, the SM120 analog of `grouped_mm_c3x_sm100.cu`. Configuration:
Added dispatch block in `scaled_mm_entry.cu` for `version_num >= 120 && version_num < 130`.
Added the `.cu` file to the existing SM12x build block in `CMakeLists.txt` (under `FP4_ARCHS`, which already sets `ENABLE_CUTLASS_MOE_SM120=1`).
CUTLASS dependency
`KernelPtrArrayTmaWarpSpecializedCooperativeSm120<2>` requires the `MainloopSm120ArrayTmaWarpSpecialized` collective specialization, which is not yet in CUTLASS 4.5. It has been contributed upstream via NVIDIA/cutlass#3280 (currently in review). This vLLM PR will compile correctly once vLLM's pinned CUTLASS revision includes that change.
Why not duplicate
Hardware validation
Validated on SM_121 hardware (NVIDIA DGX Spark, GB10, 128 GB LPDDR5X unified memory):
Result: SM120 CUTLASS grouped GEMM collective activates and produces correct outputs. Previously fell back to Triton for every MoE dispatch.
Throughput comparison (wall-clock, single-stream, MTP speculative decoding, 3 iterations)
Short-sequence improvement is the clearest signal (decode-dominated, grouped GEMM runs every forward pass). Medium/long variance is dominated by speculative decoding accept-rate noise over 3 iterations.
Update — rebased onto main (2026-06-20)
Rebased cleanly onto current `main` (post-v0.23.0). No conflicts. The two changed hunks (`_custom_ops.py` gate fix and `scaled_mm_entry.cu` dispatch block) applied without modification.
Relevant context from v0.23.0: #40923 (Marlin MoE SM 12.x native cubins) and #42027 (gelu_tanh CUTLASS/WNA16 MoE) both landed in v0.23.0, covering adjacent SM12x infrastructure. This PR addresses the remaining gap: the FP8 grouped GEMM Python gate and the missing SM120 CUTLASS kernel.
AI assistance disclosure
This fix was developed with Claude (Anthropic) AI assistance, including root cause analysis of the gate condition, derivation of the SM120 kernel configuration from the SM100 analog, and iterative compile debugging (four full Docker builds on real SM_121 hardware). All changed lines have been reviewed by the human submitter (Tyler Merritt). Build and inference validation ran on physical DGX Spark hardware.
Related CUTLASS upstream PR: NVIDIA/cutlass#3280