[Bugfix][LoRA] Fail fast on FP8 MoE + LoRA instead of cryptic Triton crash

[ldkhang1201]

Purpose

Fixes #45101. FP8-quantized MoE combined with --enable-lora crashes during engine-core init (the memory-profiling forward) with:

File ".../triton/language/semantic.py", in dot
AssertionError: Unsupported lhs dtype fp8e4nv
RuntimeError: Engine core initialization failed.

This makes that combination fail fast with a clear, actionable message instead of a cryptic Triton assertion.

Root cause

With an FP8 base MoE, the activations reaching the experts are fp8-quantized (with a separate a1q_scale). TritonExperts.apply() passes that fp8 activation buffer straight into the MoE-LoRA path (apply_w13_lora(x=hidden_states) / apply_w2_lora(x=intermediate_cache2)). The Triton MoE-LoRA shrink kernel (_fused_moe_lora_one_shot_kernel / _fused_moe_lora_small_batch_kernel) then computes tl.dot(x, lora_a).

Triton's dot only allows fp8 operands when both are fp8; LoRA adapters are bf16/fp16, so this is an unsupported mixed fp8 x bf16 dot, which trips the assertion. A naive in-kernel x.to(bf16) upcast would silence the crash but be numerically wrong (it drops a1q_scale), so this PR guards instead. Full enablement (dequantizing fp8 activations for the LoRA path) is left as a follow-up.

This only triggers with FP8 MoE + LoRA: FP8 MoE without LoRA, and bf16 MoE + LoRA, both work fine.

Fix

Guard in the shared LoRAExpertsMixin (used by the Triton, Marlin and gpt-oss expert backends), so a single check covers all of them: if the activation entering the MoE-LoRA path is fp8, raise a clear NotImplementedError telling the user to serve in bf16/fp16 or drop --enable-lora. This matches the "fail fast with a clear message" behavior requested in the issue.

Test Plan

Hardware: NVIDIA RTX PRO 6000 Blackwell (sm_120), vLLM 0.22.x, triton 3.6.0, torch 2.11+cu130.

1. Repro (issue config + LoRA): vllm serve Qwen/Qwen3.6-35B-A3B-FP8 --enable-lora --max-lora-rank 64 --enforce-eager --max-model-len 4096 --trust-remote-code
2. Negative (no false positive): allenai/OLMoE-1B-7B-0924-Instruct --enable-lora --max-lora-rank 64 (bf16 MoE + LoRA)
3. Negative (unaffected): Qwen/Qwen3.6-35B-A3B-FP8 without --enable-lora
4. New unit test: tests/lora/test_moe_lora_fp8_guard.py
5. Lint: pre-commit run ruff-check / ruff-format on changed files

Test Result

1. before: AssertionError: Unsupported lhs dtype fp8e4nv (traceback through vllm/lora/ops/triton_ops/fused_moe_lora_op.py::_fused_moe_lora_one_shot_kernel), engine init fails. after: fails fast with NotImplementedError: MoE LoRA is not supported with FP8-quantized activations ....
2. Starts cleanly (init engine ... took 4.25 s, Application startup complete) — guard does not trigger on bf16.
3. Starts cleanly and serves (2+2= → 5) — unaffected.
4. tests/lora/test_moe_lora_fp8_guard.py passes (fp8 raises, bf16/fp16/fp32 pass).
5. ruff-check + ruff-format pass.

Minimal Triton repro of the underlying restriction on sm_120 (for reference):

fp8e4nv x bf16    -> CRASH: Unsupported lhs dtype fp8e4nv
fp8e4nv x fp8e4nv -> OK
bf16 x bf16       -> OK

Not a duplicate

No open PR references #45101. Existing sm_120/sm_121 MoE PRs (#43814 CUTLASS grouped GEMM, #43333/#43341 B12x NVFP4, #43730 Marlin-MoE c_tmp clamp, #36183 sm121 NVFP4 clone) address different kernels/paths; none touch the MoE-LoRA fp8 activation guard. The issue's own hypothesis (base-MoE backend selection / VLLM_MOE_FORCE_MARLIN) turned out to be unrelated — the crash is specifically the MoE-LoRA shrink kernel, and VLLM_MOE_FORCE_MARLIN is not a real vLLM env var (the documented escape hatch is VLLM_TEST_FORCE_FP8_MARLIN, which only affects the base MoE).

AI assistance

This change was developed with AI assistance (Claude Code): reproduction, root-cause analysis, the fix, and the validation above were carried out on sm_120 hardware.

🤖 Generated with Claude Code

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