[PD] Re-add early _engine_paused gate before decode_queue / pop_boots…

[Zhichenzzz]

Summary

To fix this issue radixark/miles#1085, Re-add the early _engine_paused gate before process_decode_queue() (decode.py) and pop_bootstrapped() (prefill.py) in the PD-disaggregated event loops, fixing a regression introduced by #23887.

Background

PR	Change
#23672	First introduced if self._engine_paused: continue before process_decode_queue() / pop_bootstrapped(), gating new KV polling and new bootstrap pop during pause_generation.
#23887	Refactored both event loops; moved the pause check after those calls.

For plain PD-disagg the order swap is benign, but for PD + R3 (hierarchical cache) it re-opens a race window: once pause_generation(mode="in_place") flips _engine_paused = True, the loop still runs one more process_decode_queue() (decode side) / one more pop_bootstrapped() + scheduling lookahead (prefill side) before honoring the pause. Under concurrent KV transfer load with hicache, this is enough to corrupt the in-flight NIXL KVReceiver state, producing the symptoms originally reported in radixark/miles#1085:

Change

Add if self._engine_paused: continue immediately after process_input_requests(recv_reqs) in all four disagg event loops:

• event_loop_normal_disagg_decode
• event_loop_overlap_disagg_decode
• event_loop_normal_disagg_prefill
• event_loop_overlap_disagg_prefill

The existing post-call gate from #23887 is kept so a pause that arrives mid-iteration is still caught before the next batch runs.

Net diff: 2 files, +14 / -0.

Test plan

Validated against Qwen3.5-35B-A3B FP8 on H200, 1P1D layout, EP=4 DP=4 TP=1, --sglang-disaggregation-transfer-backend nixl, --sglang-enable-hierarchical-cache, pause_generation_mode=in_place, RANDOM_ASYNC_CONCURRENCY_PER_GPU=96, using the examples/random_async/run_random_async_3node.py agent loop from radixark/miles#1062:

Run	Groups	Weight cycles	update_weights_implementation	NIXL exceptions	Decode-transfer failures	EXIT
1	72	2	9.6 s, 10.0 s	0	0	0
2	72	2	9.6 s, 10.5 s	0	0	0

R3 prefix cache hit rate ~84 % across both runs. Each run completes two full pause / weight-transfer / continue cycles without any decode-side NIXL KVReceiver failures.

Motivation

Modifications

Accuracy Tests

Speed Tests and Profiling

Checklist

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