drivers: usb: udc: enable UDC on Infineon pse84 devices#106841
drivers: usb: udc: enable UDC on Infineon pse84 devices#106841teburd merged 4 commits intozephyrproject-rtos:mainfrom
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| num-out-eps = <8>; | ||
| ghwcfg1 = <0x00000000>; | ||
| ghwcfg2 = <0x228fe052>; | ||
| ghwcfg4 = <0xe2103a20>; |
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Thank you for the contribution! Would it be possible to also obtain the gsnspid= and gwhcfg3= values?
This will help with this PR:
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Aye, here they are:
gwhcfg3 = 0x1a4f80e8
gsnipsid = 0x4f54420a
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I would also like to ask for fifo sizes to be used for #99510.
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Sure, here they are -
g-rx-fifo-size = 543
g-np-tx-fifo-size = 64
g-tx-fifo-size = 768 768 768 768 768 768 768 752
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I thought this - #106846 - was a bug in the UDC driver, but it's actually in this MR instead. Will update this PR once I resolve this edit - this was a mismatch between the ghwcfg4 and num-x-eps, which I've since resolved |
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| static int usbhs_ifx_phy_enable(const struct device *dev) | ||
| { | ||
| const struct udc_dwc2_config *const config = dev->config; | ||
| USBHS_Type *base = (USBHS_Type *)config->base; |
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What is USBHS_Type? Why do you think type conversion from config->base is okay?
What are base->SS.*?
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USBHS_Type is a register map structure for the Synopsys registers + Infineon's wrapper registers, specifically with the Infineon registers placed after the Synopsys ones. Added a couple comments documenting this. With this context, are you still concerned about this casting?
SS points to the register map structure for the Infineon wrapper registers.
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@jfischer-no I saw you resolved most of the threads in this PR. If these two were left open because they are unsatisfied, can you clarify what you're looking for?
| #define QUIRK_INFINEON_USBHS_DEFINE(n) \ | ||
| \ | ||
| static const struct usb_ifx_mmio_config usb_ifx_mmio_##n = { \ | ||
| .peri_inst = DT_INST_PROP(n, mmio_peri_inst), \ | ||
| .grp_num = DT_INST_PROP(n, mmio_peri_group), \ | ||
| .usb_bit_pos = DT_INST_PROP(n, mmio_reg_bit_pos), \ | ||
| .clk_src = DT_INST_PROP(n, mmio_peri_hf_src), \ | ||
| .clk_div = DT_INST_PROP(n, mmio_peri_div), \ | ||
| }; \ | ||
| \ | ||
| static int usbhs_ifx_mmio_init_##n(const struct device *dev) \ | ||
| { \ | ||
| Cy_SysClk_PeriGroupSlaveInit(usb_ifx_mmio_##n.peri_inst, usb_ifx_mmio_##n.grp_num, \ | ||
| usb_ifx_mmio_##n.usb_bit_pos, \ | ||
| usb_ifx_mmio_##n.clk_src); \ | ||
| Cy_SysClk_PeriGroupSetDivider(((usb_ifx_mmio_##n.peri_inst) << 8) | \ | ||
| (usb_ifx_mmio_##n.grp_num), \ | ||
| (usb_ifx_mmio_##n.clk_div)); \ | ||
| return 0; \ | ||
| } \ | ||
| \ | ||
| const struct dwc2_vendor_quirks dwc2_vendor_quirks_##n = { \ | ||
| .init = usbhs_ifx_mmio_init_##n, \ | ||
| .pre_enable = usbhs_ifx_phy_enable, \ | ||
| .disable = usbhs_ifx_phy_disable, \ | ||
| .caps = usbhs_ifx_set_caps}; | ||
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| DT_INST_FOREACH_STATUS_OKAY(QUIRK_INFINEON_USBHS_DEFINE) |
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Please keep the style of other quirks/driver/subsystem.
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I thought I had - may I ask what looks wrong? I saw the end of my dwc2_vendor_quirks structure was odd from a sloppy line delete and fixed that
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| # This binding describes additional information required to use | ||
| # the Synopsys DesignWare OTG USB 2.0 controller IP on Infineon | ||
| # boards. In the case of this IP, the Peri MMIO group information | ||
| # is required. |
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Is there a reason to not make it part of the actual description? (Also note that you can split title: and description:)
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No reason - moved it over. I kept it as all "description" though to match the neighboring bindings.
| # The below example shows using Peri 1 MMIO 3, sourced from CLK_HF1 and using | ||
| # a divider of 3. Peri MMIO dividers also require a specific target interconnect | ||
| # bit mask, a bit whose position is stored in mmio-peri-bit-pos. This bit value | ||
| # must come from some Infineon documentation, e.g. a TRM or through working with | ||
| # the Infineon Device Configurator tool. | ||
| # The only mmio-peri value that can be configured is mmio-peri-div. The other | ||
| # four values are hardwired on the device. |
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Same, make this a C-style comment before the Devicetree snippet so that this is rendered in the documentation
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Thanks for pointing this out - moved/formatted it and generated the docs to confirm it's there now
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This commit adds a new binding for using Infineon USB. This builds off the existing Synopsys Designware USB 2.0 binding Signed-off-by: Zayne Stites <Zayne.Stites@infineon.com>
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Add Infineon vendor quirks to the UDC DW2 implementation. This ties to the infineon,usbhs binding. Signed-off-by: Zayne Stites <Zayne.Stites@infineon.com>
Add usbhs instance to kit_pse84_eval dtsi files. This device has one usb block, but due to it being a multi-core trustzone-capable device we have a couple addresses (s & ns) and two sets of interrupts (cm33 & cm55). Signed-off-by: Zayne Stites <Zayne.Stites@infineon.com>
Add usbd to kit_pse84_eval board supported driver list. Additionally, set the usbhs instance to default to "okay" with the alias zephyr_udc0, per usb device standard Signed-off-by: Zayne Stites <Zayne.Stites@infineon.com>
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Force push just moved the #if COMPAT(Infineon,usbhs) in udc_dwc2.h to be in alphabetical order, which will hopefully also resolve the merge conflict as a side effect |
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Added vendor quirks to the driver to enable UDC on Infineon pse84 devices, as well as related dtsi / binding additions to enable it on the boards. This builds off the existing Synopsys USB IP implementation.
Note - this requires #106840 to get the UID.