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drivers: usb: udc: enable UDC on Infineon pse84 devices#106841

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teburd merged 4 commits intozephyrproject-rtos:mainfrom
stites-infineon:topic/pse84-udc-support
Apr 29, 2026
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drivers: usb: udc: enable UDC on Infineon pse84 devices#106841
teburd merged 4 commits intozephyrproject-rtos:mainfrom
stites-infineon:topic/pse84-udc-support

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Added vendor quirks to the driver to enable UDC on Infineon pse84 devices, as well as related dtsi / binding additions to enable it on the boards. This builds off the existing Synopsys USB IP implementation.

Note - this requires #106840 to get the UID.

num-out-eps = <8>;
ghwcfg1 = <0x00000000>;
ghwcfg2 = <0x228fe052>;
ghwcfg4 = <0xe2103a20>;
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Thank you for the contribution! Would it be possible to also obtain the gsnspid= and gwhcfg3= values?

This will help with this PR:

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Aye, here they are:
gwhcfg3 = 0x1a4f80e8
gsnipsid = 0x4f54420a

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I would also like to ask for fifo sizes to be used for #99510.

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Sure, here they are -
g-rx-fifo-size = 543
g-np-tx-fifo-size = 64
g-tx-fifo-size = 768 768 768 768 768 768 768 752

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stites-infineon commented Apr 8, 2026

I thought this - #106846 - was a bug in the UDC driver, but it's actually in this MR instead. Will update this PR once I resolve this

edit - this was a mismatch between the ghwcfg4 and num-x-eps, which I've since resolved

Comment thread drivers/usb/udc/udc_dwc2_vendor_quirks.h Outdated
Comment thread drivers/usb/udc/udc_dwc2_vendor_quirks.h Outdated
@stites-infineon stites-infineon force-pushed the topic/pse84-udc-support branch from da89e04 to 7de0a30 Compare April 8, 2026 21:48
@zephyrbot zephyrbot requested a review from teburd April 8, 2026 21:49
@stites-infineon stites-infineon force-pushed the topic/pse84-udc-support branch 2 times, most recently from c4450b2 to 63fd459 Compare April 9, 2026 20:42
Comment thread dts/bindings/usb/infineon,usbhs.yaml
Comment thread dts/bindings/usb/infineon,usbhs.yaml Outdated
Comment thread drivers/usb/udc/udc_dwc2_vendor_quirks.h Outdated
static int usbhs_ifx_phy_enable(const struct device *dev)
{
const struct udc_dwc2_config *const config = dev->config;
USBHS_Type *base = (USBHS_Type *)config->base;
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What is USBHS_Type? Why do you think type conversion from config->base is okay?
What are base->SS.*?

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USBHS_Type is a register map structure for the Synopsys registers + Infineon's wrapper registers, specifically with the Infineon registers placed after the Synopsys ones. Added a couple comments documenting this. With this context, are you still concerned about this casting?

SS points to the register map structure for the Infineon wrapper registers.

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@jfischer-no I saw you resolved most of the threads in this PR. If these two were left open because they are unsatisfied, can you clarify what you're looking for?

Comment on lines +774 to +801
#define QUIRK_INFINEON_USBHS_DEFINE(n) \
\
static const struct usb_ifx_mmio_config usb_ifx_mmio_##n = { \
.peri_inst = DT_INST_PROP(n, mmio_peri_inst), \
.grp_num = DT_INST_PROP(n, mmio_peri_group), \
.usb_bit_pos = DT_INST_PROP(n, mmio_reg_bit_pos), \
.clk_src = DT_INST_PROP(n, mmio_peri_hf_src), \
.clk_div = DT_INST_PROP(n, mmio_peri_div), \
}; \
\
static int usbhs_ifx_mmio_init_##n(const struct device *dev) \
{ \
Cy_SysClk_PeriGroupSlaveInit(usb_ifx_mmio_##n.peri_inst, usb_ifx_mmio_##n.grp_num, \
usb_ifx_mmio_##n.usb_bit_pos, \
usb_ifx_mmio_##n.clk_src); \
Cy_SysClk_PeriGroupSetDivider(((usb_ifx_mmio_##n.peri_inst) << 8) | \
(usb_ifx_mmio_##n.grp_num), \
(usb_ifx_mmio_##n.clk_div)); \
return 0; \
} \
\
const struct dwc2_vendor_quirks dwc2_vendor_quirks_##n = { \
.init = usbhs_ifx_mmio_init_##n, \
.pre_enable = usbhs_ifx_phy_enable, \
.disable = usbhs_ifx_phy_disable, \
.caps = usbhs_ifx_set_caps};

DT_INST_FOREACH_STATUS_OKAY(QUIRK_INFINEON_USBHS_DEFINE)
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Please keep the style of other quirks/driver/subsystem.

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I thought I had - may I ask what looks wrong? I saw the end of my dwc2_vendor_quirks structure was odd from a sloppy line delete and fixed that

Comment thread samples/subsys/usb/testusb/app.overlay
@stites-infineon stites-infineon force-pushed the topic/pse84-udc-support branch from 63fd459 to dbbc186 Compare April 16, 2026 20:48
@zephyrbot zephyrbot requested a review from jfischer-no April 16, 2026 20:50
@stites-infineon stites-infineon force-pushed the topic/pse84-udc-support branch from dbbc186 to 3a74201 Compare April 16, 2026 23:23
Comment thread dts/bindings/usb/infineon,usbhs.yaml Outdated
Comment on lines +7 to +10
# This binding describes additional information required to use
# the Synopsys DesignWare OTG USB 2.0 controller IP on Infineon
# boards. In the case of this IP, the Peri MMIO group information
# is required.
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@kartben kartben Apr 23, 2026

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Is there a reason to not make it part of the actual description? (Also note that you can split title: and description:)

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No reason - moved it over. I kept it as all "description" though to match the neighboring bindings.

Comment thread dts/bindings/usb/infineon,usbhs.yaml Outdated
Comment on lines +47 to +53
# The below example shows using Peri 1 MMIO 3, sourced from CLK_HF1 and using
# a divider of 3. Peri MMIO dividers also require a specific target interconnect
# bit mask, a bit whose position is stored in mmio-peri-bit-pos. This bit value
# must come from some Infineon documentation, e.g. a TRM or through working with
# the Infineon Device Configurator tool.
# The only mmio-peri value that can be configured is mmio-peri-div. The other
# four values are hardwired on the device.
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Same, make this a C-style comment before the Devicetree snippet so that this is rendered in the documentation

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Thanks for pointing this out - moved/formatted it and generated the docs to confirm it's there now

Comment thread boards/infineon/kit_pse84_eval/kit_pse84_eval_m33.yaml Outdated
Comment thread samples/subsys/usb/cdc_acm/app.overlay Outdated
@stites-infineon stites-infineon force-pushed the topic/pse84-udc-support branch from 3a74201 to f4687d7 Compare April 24, 2026 20:10
@zephyrbot zephyrbot requested a review from jfischer-no April 24, 2026 20:12
Comment thread dts/bindings/usb/infineon,usbhs.yaml
This commit adds a new binding for using Infineon USB.  This builds
off the existing Synopsys Designware USB 2.0 binding

Signed-off-by: Zayne Stites <Zayne.Stites@infineon.com>
@stites-infineon stites-infineon force-pushed the topic/pse84-udc-support branch 2 times, most recently from 2a91bc2 to 8a03a77 Compare April 24, 2026 22:50
@zephyrbot zephyrbot requested a review from jfischer-no April 24, 2026 22:51
Add Infineon vendor quirks to the UDC DW2 implementation.  This
ties to the infineon,usbhs binding.

Signed-off-by: Zayne Stites <Zayne.Stites@infineon.com>
Add usbhs instance to kit_pse84_eval dtsi files.  This
device has one usb block, but due to it being a multi-core
trustzone-capable device we have a couple addresses (s & ns)
and two sets of interrupts (cm33 & cm55).

Signed-off-by: Zayne Stites <Zayne.Stites@infineon.com>
Add usbd to kit_pse84_eval board supported driver list.  Additionally,
set the usbhs instance to default to "okay" with the alias zephyr_udc0,
per usb device standard

Signed-off-by: Zayne Stites <Zayne.Stites@infineon.com>
@stites-infineon stites-infineon force-pushed the topic/pse84-udc-support branch from 8a03a77 to 091d7a9 Compare April 27, 2026 15:45
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Force push just moved the #if COMPAT(Infineon,usbhs) in udc_dwc2.h to be in alphabetical order, which will hopefully also resolve the merge conflict as a side effect

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@teburd teburd merged commit d55c345 into zephyrproject-rtos:main Apr 29, 2026
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area: Boards/SoCs area: Devicetree Binding PR modifies or adds a Device Tree binding area: Samples Samples area: USB Universal Serial Bus platform: Infineon Infineon Technologies AG

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7 participants