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dts: bindings: dwc2: add extra hardware registers and devicetree entries#103015

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dts: bindings: dwc2: add extra hardware registers and devicetree entries#103015
josuah wants to merge 1 commit intozephyrproject-rtos:mainfrom
josuah:dwc2_bindings

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@josuah josuah commented Jan 27, 2026

Very small PR to add extra hardware registers that can later be used inside drivers.

Given this has no dependency, I thought I might as well submit it directly on main so it's possible to use it from everywhere (device, host).

The registers were obtained by logging their value out.

@josuah josuah closed this Jan 27, 2026
@josuah josuah reopened this Jan 27, 2026
@josuah josuah marked this pull request as ready for review January 27, 2026 23:43
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josuah commented Jan 27, 2026

Ping @roma-jam for review in case you was interested.

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Thanks for the ping @josuah,

I saw it in your PR: #95723
And I also took it from your and introduced in here: #102966

From my side it seems that we will need it anyway so we can merge it separately.

Comment thread dts/bindings/usb/snps,dwc2.yaml Outdated
type: int
description: |
Value of the GSNPSID register, used to identify the version of the core
and avoid mismatch by checking the register at runtime.
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I would remove the "and avoid mismatch by checking the register at runtime." as it implies how it is used.

In general, I am all in for having gsnpsid defined here, because there is benefit in knowing the core version at compile time when it comes to enabling workarounds (workaround code can be not compiled if core is not subject to the bug).

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You are right best describe the hardware only. I remember something involving testing gsnpsid in Linux for enabling/disabling workarounds.
I just pushed the change.

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josuah commented Feb 18, 2026

Force-push:

  • Rebase on main to fix merge conflict: Content moved to dts/vendor/nordic/nrf54lm20_a_b.dtsi common to both a and b chip revisions.

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tmon-nordic
tmon-nordic previously approved these changes Feb 19, 2026
wmrsouza
wmrsouza previously approved these changes Feb 19, 2026
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josuah commented Mar 11, 2026

Trying a 4.4 milestone in case this is trivial enough.

Otherwise other PRs can just rebase on top of it.

@jfischer-no jfischer-no removed this from the v4.4.0 milestone Mar 11, 2026
@josuah josuah linked an issue Mar 11, 2026 that may be closed by this pull request
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josuah commented Mar 12, 2026

@roma-jam it will be convenient if you could rebase #102966 on top of this one to avoid having to duplicate the entire tree and have only one chain of PRs to present to reviewers. Would that make sense?

P.S. I updated this issue with the dependencies as I understand them: #102931

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Now that Synaptics SR100 is merged, you can add

gsnpsid = <0x5532430a>;
ghwcfg3 = <0x0c78c468>;

to dts/arm/synaptics/sr100.dtsi. The values are taken from #100172 (comment)

@josuah josuah dismissed stale reviews from wmrsouza and tmon-nordic via c028e4e March 30, 2026 20:19
@josuah josuah force-pushed the dwc2_bindings branch 2 times, most recently from c028e4e to b80daf6 Compare March 30, 2026 20:20
Add 'gsnpsid' and 'ghwcfg3' to DWC2 USB peripheral in order to check
that they are as expected at runtimne, which the host driver can use.

Signed-off-by: Josuah Demangeon <josuah.demangeon@nordicsemi.no>
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josuah commented Mar 30, 2026

Force-push:

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Hi @josuah,

it will be convenient if you could rebase #102966 on top of this one to avoid having to duplicate the entire tree and have only one chain of PRs to present to reviewers. Would that make sense?

thanks, I cherry-picked the commit from this PR to my PR in here: #102967.

Comment thread dts/arm/syna/sr100.dtsi
Comment on lines +192 to +195
gsnpsid = <0x5532430a>;
ghwcfg1 = <0x00000000>;
ghwcfg2 = <0x02882054>; // 8 endpoints, dynamic sizing
ghwcfg3 = <0x0c78c468>;
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As for the other partial UHC DWC2 PRs, this change should be included in UHC DWC2 PR #102967. Also, there is no need to provide what is available at runtime through DT. ghwcfg1, ghwcfg2, and ghwcfg4 are workarounds for the peculiarities of nRF54 family.

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Ok, so removing ghwcfg3 and reading this information from hardware registers instead.

Should there still be gsnpsid?

If not, then it is possible to use gsnpsid != 0 to detect when the DWC2 core is not available (i.e. in ESP32-S3 before the PHY is powered on).

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area: Boards/SoCs area: Devicetree Binding PR modifies or adds a Device Tree binding area: USB Universal Serial Bus area: Xtensa Xtensa Architecture platform: ESP32 Espressif ESP32 platform: nRF Nordic nRFx

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DWC2 USB Host controller (UHC)

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