[Kernel] SM 12.x blockwise FP8: swizzle the CTA raster when the weight exceeds the L2 - #55180
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WalkthroughThe SM120 FP8 blockwise GEMM path raises the activation threshold for swizzling from 12 MiB to 14 MiB. The selected swizzle size now flows through blockwise dispatch into ChangesSM120 FP8 blockwise GEMM swizzle scheduling
Estimated code review effort: 2 (Simple) | ~10 minutes Merge Risk: ⚪ Minimal · up to This change adjusts when SM120 FP8 blockwise GEMM uses CTA swizzling, retaining default scheduling for smaller activation slabs and cache-resident weights. No concrete merge-blocking correctness, stability, or deployment risk is identified. 🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
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`@csrc/libtorch_stable/quantization/w8a8/cutlass/c3x/scaled_mm_blockwise_sm120_fp8.cu`:
- Line 44: Validate that k is greater than zero before blockwise_fp8_chunk_rows
computes the chunk row count, using the existing
dispatch_scaled_mm/blockwise_fp8_should_chunk path and an appropriate
STD_TORCH_CHECK; alternatively, explicitly return the defined empty-K result
before division. Ensure no division by zero occurs.
In `@tests/kernels/quantization/test_cutlass_scaled_mm.py`:
- Line 771: Restrict the GB202-sized (147 MB) parameter case added near the
parameter list to SM 12.x devices, or move it into a dedicated large-GPU test,
so the expensive FP32 baseline and chunked reference do not run for SM 9.x or SM
10.x; preserve the existing general FP8 cases and gating behavior.
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csrc/libtorch_stable/quantization/w8a8/cutlass/c3x/scaled_mm_blockwise_sm120_fp8.cutests/kernels/quantization/test_cutlass_scaled_mm.py
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…weight exceeds the L2
On SM 12.x parts with a small L2 (GB10: 24 MiB) the blockwise FP8 GEMM
loses most of its throughput once M spans many tile rows, because the
weight operand is re-streamed from DRAM per tile row: on a GB10 a
16384x2560 FP8 weight runs at 163 TFLOPS at M=4096 but 95 at M=8192 and
51 at M=16384, while the same GEMM issued as 4096-row launches stays at
~160 TFLOPS at every M. cuBLASLt's row-wise FP8 path degrades the same
way; its per-tensor path does not.
Inside cutlass_scaled_mm_blockwise_sm120_fp8, issue the GEMM in 4096-row
launches when M > 4096 and the weight (N*K bytes) exceeds the device L2.
A and the output are row-range views written in place; each chunk's
activation scales are re-laid out in the kernel's column-major layout,
which the kernel derives from its own M. The dispatch stays inside the op,
so the compiled model graph sees one opaque op with symbolic M. Parts
whose L2 holds the weight are not chunked. The chunked result is
bit-identical to the single launch.
Tests: bit-equality against a row-chunked reference and the fp32
tolerance baseline at M in {4096, 8193, 12288}; one compiled
dynamic-shape graph serving all three.
Co-authored-by: Claude <noreply@anthropic.com>
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_011SuBgdp87NbfLbiigmzn1z
Signed-off-by: Jürgen Schmied <juergenschmied70@gmail.com>
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I think a better fix would be a proper kernel with GB10-specific CTA swizzling config. Not sure if it's possible to do it with Cutlass high-level API. Separately I have a Triton and CuteDSL kernel for this tuned for 5090. Should be straight-forward to tweak it for GB10. You can give it a try.
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Agreed that a raster/CTA-swizzle config tuned for the 24 MiB L2 is the better kernel; this PR is the exact-numerics step that recovers most of it without touching the mainloop (chunked = bit-identical to a single launch, 155–170 TFLOPS at every M on GB10 vs 51–95 collapsed). The two are not exclusive — a swizzled kernel would make the gate here a no-op on GB10, which is fine. I will try your Triton and CuteDSL kernels at the GB10 shapes (M ∈ {4096, 8192, 16384}, the 16384×2560 / 5120×5120 / 10240×2560 blockwise weights, 128×128 scales) against the numbers in the PR body; I have the harness from this PR's measurements. One caveat from earlier on this box: the CuteDSL MoE path refused sm_121 ( |
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You were right, and it is reachable through the high-level API:
5120×5120 goes further (74 → 163–168 TF at M ≥ 6144, chunking gave 153–155); raster order AlongM/AlongN is within noise of the heuristic. The only cost is at M ≤ 4096 while the weight still fits the L2 (155 vs 170 on the widest weight), so the gate stays the same as before (weight bytes > Two things this suggests beyond the PR: CUTLASS's default of |
…nking M Replace the M-chunking loop with the CUTLASS persistent tile scheduler's max_swizzle_size (= 8) once the FP8 weight exceeds the device L2 and M > 4096. Same effect as the chunked launches (150-168 TFLOPS at every M on GB10 vs 52-95 collapsed), bit-identical to the default order, and the whole change is one scheduler argument: no chunk-size heuristic, no scale re-layout, no extra launches. Reviewer suggestion (gau-nernst): a proper GB10-tuned raster rather than chunking; measured here via TileSchedulerArguments, which cutlass_gemm_caller already accepts. AI assistance: the measurement harness and drafts were produced with Claude Code; every line was reviewed by the author. Co-authored-by: Claude <noreply@anthropic.com> Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_011SuBgdp87NbfLbiigmzn1z Signed-off-by: Jürgen Schmied <juergenschmied70@gmail.com>
jschmied
changed the title
…balanced test slices - Gate the swizzle on A's byte count (>= 12 MiB) instead of M > 4096: at M=4096 the 5120x5120 weight (20 MiB of A) already collapses (117 TFLOPS default, 160 swizzled) while 16384x2560 (10 MiB of A) is still faster in the default order (165-170 vs 149-155); every shape at M=6144 (15 MiB) gains. The threshold is empirical and documented. - The exact-equality reference slices M into balanced <= 4096-row launches so no slice drops into the M <= 256 / M <= 64 kernel configurations (4097 -> 2049 + 2048, not 4096 + 1). - Soften the raster comment: the scheduler groups nearby M/N tiles, the traversal order itself is its heuristic. Co-authored-by: Claude <noreply@anthropic.com> Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_011SuBgdp87NbfLbiigmzn1z Signed-off-by: Jürgen Schmied <juergenschmied70@gmail.com>
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Follow-up pushed (gate + test oracle):
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The verification sweep of the pushed code adds the M=5120 point on 16384x2560 (12.5 MiB of A): default 166 TFLOPS, swizzled 153, while M=6144 (15 MiB) is 137 vs 153. The crossover for K=2560 is between 12.5 and 15 MiB; 14 MiB keeps every measured decision right, including 5120x5120 at M=4096 (20 MiB: 117 -> 160). Co-authored-by: Claude <noreply@anthropic.com> Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_011SuBgdp87NbfLbiigmzn1z Signed-off-by: Jürgen Schmied <juergenschmied70@gmail.com>
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… two prefill-sized cases to the existing blockwise test Review: correctness is CUTLASS's; two cases in test_cutlass_fp8_blockwise_scale_gemm cover the swizzled path (weight > L2, activation slab >= 14 MiB) and the odd-M dispatch, without new test functions. Co-authored-by: Claude <noreply@anthropic.com> Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_011SuBgdp87NbfLbiigmzn1z Signed-off-by: Jürgen Schmied <juergenschmied70@gmail.com>
The activation-slab term kept the default order below M ~5.7k; a sweep over ten N/K shapes x M 2048-16384 on GB10 shows the swizzled order equal or up to 3.3x faster everywhere the weight exceeds the L2 except a narrow band around M=4096 on the 2560-wide weights (-4..-8%), and worse than the default order only where the weight fits the L2 (2560x6144), which the remaining condition excludes. All cells bit-identical to the default order. Co-authored-by: Claude <noreply@anthropic.com> Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_011SuBgdp87NbfLbiigmzn1z Signed-off-by: Jürgen Schmied <juergenschmied70@gmail.com>
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Thanks — both done or measured: 2. Tests. Dropped the two dedicated test functions and the sliced reference (−103 lines). 1. The heuristic, sm120, and more shapes. I have no sm120 card, so here is what I can say and what I measured:
bit-identical everywhere: True Reading it: the swizzled order is flat at 150–174 TF at every M and every shape; the default order is the erratic one (54 TF at M ≥ 6144 on 8192×8192, 50–53 on 14336×4096 and 32768×4096 from M = 6144–8192). Where the weight exceeds the L2 the swizzle is equal or up to 3.3× faster except one narrow band, M = 4096 on the 2560-wide weights (0.92–0.98) — and that band is the only thing my activation-slab term ever protected, while costing 12 % at M = 2048 on 16384×2560. Where the weight fits the L2 (2560×6144, 4096×4096) the swizzle is neutral to −8 %, which Data and harness: |
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/ci run |
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✅ Triggered Buildkite CI #87391 for commit |
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Server-level numbers for the swizzle, since the review asked what it does end to end rather than in a microbench. Setup: Qwen3.8-Flash-Next (FP8-mixed checkpoint), one GB10, vLLM main (dev401) with this PR's kernel loaded as an
At 16k chunks the gate opens for the projections above the 24 MiB L2 ( Kernel-level, from a torch-profiler trace of one 29k prefill per arm (16k chunks): the blockwise-FP8 GEMM kernel One caveat for anyone reproducing with an overlay rather than the built kernel: vLLM's compile cache does not key on |
Unrelated to this PR's change. The repo-wide pre-commit runs clang-format with --all-files, and scaled_mm_blockwise_sm120_fp8.cu (added by vllm-project#55180, untouched here) fails the pinned clang-format v21.1.2 on a comment that needs reflowing. This reflows that single comment so the pre-commit gate passes; no functional change. Maintainers: happy to drop this commit if you prefer to fix it upstream on main instead. Signed-off-by: shaolila <shaolila@buaa.edu.cn>
…t exceeds the L2 (vllm-project#55180) Signed-off-by: Jyotirmoy Roy <jyotirmoyroy649@gmail.com>
3 participants
Purpose
On SM 12.x parts whose L2 does not hold the FP8 weight operand (GB10 / DGX Spark: 24 MiB L2), the CUTLASS blockwise-FP8 GEMM (
CutlassFp8BlockScaledMMKernel, 128×128 weight blocks, 1×128 activation scales) loses most of its throughput once M spans many rows of tiles: the default CTA raster revisits each weight tile too far apart and the weight is re-streamed from DRAM. Measured on GB10 (torch.cuda.Eventtiming, 5×10 launches, median):This is a prefill-time cost on every FP8-blockwise model served on these parts (8k–32k-token prompts).
Changes
csrc/libtorch_stable/quantization/w8a8/cutlass/c3x/scaled_mm_blockwise_sm120_fp8{.cu,_dispatch.cuh}: when the weight (N·K bytes) exceeds the device L2 (cudaDeviceProp::l2CacheSize, read once) and the activation slab (M·K bytes) is at least 14 MiB, the launch sets the persistent tile scheduler'smax_swizzle_size = 8through theTileSchedulerArgumentsthatcutlass_gemm_calleralready accepts. The swizzled raster visits the M tiles of one weight column group before moving on, so weight tiles are re-read from L2. The result is bit-identical to the default order (each output tile's K-reduction is unchanged). Everything else is untouched; parts whose L2 holds the weight (RTX PRO 6000 Blackwell / GB202, 96–128 MiB) keep the default order, as do launches whose activation slab is below 14 MiB, where the default order is still marginally faster on GB10 (16384×2560 at M=4096: 165–170 vs 149–155 TFLOPS, at M=5120: 166 vs 153) — while 5120×5120 at M=4096 (20 MiB of A) already collapses without the swizzle (117 vs 160). The threshold is empirical, from the table below.The first revision of this PR chunked M into separate launches instead; reviewer @gau-nernst suggested a proper raster, and the scheduler argument turns out to give the same recovery with none of the machinery (no chunk loop, no scale re-layout, no size heuristic).
Measurements (GB10, CUTLASS v4.7.1, two starts, all bit-identical to the default order)
Raster order (
Heuristic/AlongM/AlongN) is within noise at swizzle 8; the heuristic is kept.Test Plan
tests/kernels/quantization/test_cutlass_scaled_mm.py::test_cutlass_fp8_blockwise_large_m: M ∈ {4096, 4097, 8193, 12288} × weights of 5 MB (control), 25 MiB and 42 MB, plus one 147 MB weight (SM 12.x only): against the dequantized fp32 baseline, and — on SM 12.x — bit-identical to the same GEMM issued as balanced ≤4096-row slices in the default order (balanced so every slice stays in the same kernel configuration).::test_cutlass_fp8_blockwise_compiled_dynamic_m: onetorch.compilegraph with symbolic M serves both sides of the threshold (frame_count stays 1) and matches eager.Test Result
GB10 (sm_121), CUDA 13.0: all of the above pass; the bit-identity sweep is 30/30.
AI assistance: the measurement harness, drafts and this description were produced with Claude Code (Claude Fable 5.1); every line of the change was reviewed by the author.
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