[Kernel] Make persistent_topk deterministic

[jschmied]

Purpose

persistent_topk (the QSA / sparse-indexer block selection, csrc/libtorch_stable/persistent_topk.cuh) returns a different result for identical inputs from call to call: the order always varies, and when more keys share the threshold value than the candidate buffers hold, the selected set varies too. Downstream, the sparse attention sums the selected keys in output order, so greedy decoding of Qwen3.8-Flash-Next forks between identical requests (#54521; bit-level bisection in our thread on #53142: the indexer is the first module whose output differs with identical inputs, and an exact selection makes a 7.5k-token forward bit-identical).

Cause: output slots are handed out by atomicAdd in thread-arrival order, and exact-key ties at the last radix round are taken first-come.

Where the measurements are

The thread is long. The comments that carry data, so you do not have to read the rest:

what	where
End-to-end server A/B, three starts per arm — no measurable TTFT or per-turn cost	09-04
Alternatives measured on request: top_k_per_row_decode (0/56 shapes deterministic), and a correction retracting my first comparison of it	09-07
torch.topk and the MSA Triton bitonic top-k: both deterministic, 4.4–9.9× and 5.0–35.6×	09-07
The ≥128 KiB filtered path, measured on rented H100 and A100, and partly fixed	09-07
The rows > 32 routing question — asked, then measured; the dispatch is sound	09-07
Independent confirmations from two other people's hardware	09-08
#55872's FlashInfer backend tested here: does not start on sm_121	09-08

Changes

• Single-CTA rows (decode / medium paths, and the float instantiation of the filtered kernel): det_select_row — a radix select that rescans the row per key byte, so there are no candidate buffers to truncate and the pivot is exact, followed by one index-ordered block scan that emits everything above the pivot and then the lowest-index elements equal to it. Both groups come out in ascending index order, so the row is two sorted runs and a single merge finishes it.
• Multi-CTA rows (> RADIX_THRESHOLD): the radix rounds are kept; the emission becomes deterministic — per-CTA >/== counts published before the barrier, slots from a prefix over CTAs, both groups ranked by index. CTA c covers a lower index range than CTA c+1, so each group is one ascending run across the whole row and CTA 0 merges them.
• A radix pass is skipped when the threshold bin holds exactly the number of slots still unfilled: the remaining key bytes cannot change the answer. The output is then a single run, which the merge returns from immediately.
• The 256-bin suffix sum and the threshold search run in one warp (lane-local serial sums, then a Hillis-Steele suffix scan over the 32 lane totals), removing 32 __syncthreads() per call. The emission packs its two flags into a single BlockScan.
• RADIX_THRESHOLD 32768 → 16384: the single-CTA select caches the row's ordered keys at 4 bytes per element, so 32,768 elements want 128 KB against this device's 101,376 B opt-in; rows above the threshold take the multi-CTA path instead. This is a capacity constraint, not a claim that either path is faster — the measured crossover is row-count dependent, see Limitations. (Corrected 2026-09-08: this bullet previously read "the deterministic multi-CTA path is cheaper than the single-CTA select above 16k", which the Limitations section already contradicted.)
• Launcher: caps the dynamic shared-memory request at sharedMemPerBlockOptin − static __shared__ (needed on sm_121, 99 KB opt-in), and applies its chunk_size >= TopK check only on the cooperative path.
• Output contract is ascending index order, identical across calls, equal to top-k by value desc / index asc.

topk_histogram_4096.cuh is unchanged (its float instantiation is no longer reached).

Cost (GB10 / sm_121, 5 × 50 launches, median µs, ratio to the unmodified kernel)

rows	n	k	earlier revision	at 995cd99
1	4,096	2048	4.31×	1.20×
1	8,192	2048	2.95×	1.00×
1	32,768	2048	1.82×	1.10×
1	65,536	2048	2.36×	1.40×
64	1,024	512	1.66×	0.74×
64	8,192	2048	3.10×	1.10×
64	32,768	2048	2.25×	1.32×
24	32,768	2048	3.72×	2.14×

Whole grid 0.74–2.14× at 995cd99, against 1.3–4.3× when this PR was opened. Two later commits
move it again — see "Two follow-up commits" below. The change came from removing
work: the final sort was ordering data the emission had already ordered, the bin scan cost 32 block
syncs per call, the last radix passes frequently cannot change the answer, and the emission can write
straight into final positions. End to end there is no cost — server-level A/B, three starts per arm,
numbers here.

One regression, disclosed rather than hidden — since fixed. Cells at n ≤ 16,384 with k = 2048
were about 5 % slower than an intermediate revision of this branch — 8 rows / 16,384 / 2048 was
18.5 µs → 19.4 µs, reproducible to ±0.1 over three fresh processes. (Resolved by the blocked
emission below: that cell now measures 12.4 µs, 0.75× stock.) At the time I could not explain it: a build without the
signed-zero fix measures the same, cuobjdump shows identical registers (64) and static shared memory
(5,280 B), the launch geometry for that shape is unchanged, and moving the multi-CTA block out of line
made it worse. 18 of 43 cells improve in absolute time and the grid range narrows at both ends, so
the trade is net positive, but the 5 % is real.

Two follow-up commits (2026-09-08)

Both are correctness-gated: the self-consistency/exactness suite reports FAILS: 0 on each before
any timing is taken, and neither can change the selected set or its order.

• Blocked 4-item emission. The emission ran one cub::BlockScan + __syncthreads() per
  N_THREADS elements — 16 of each per row at n = 16,384. Giving each thread four consecutive
  indices makes a tile 4·N_THREADS and cuts that 4×. Blocked (not striped) ownership is what keeps
  pos = g + min(e, fin) valid: it is a pure function of index, pivot and fin.
• RADIX_THRESHOLD 16,384 → 22,016, the shared-memory caching bound (see Limitations).

Measured on GB10, four builds, interleaved arms, three bench starts each, 48 cells spanning
n = 8,192…65,536 and including the widths where routing flips. Ratio to the unmodified kernel over
the 43 cells where the stock control is tight — the 5 excluded cells sit at 6–14 µs where a ~4 µs
timer jitter dominates; the stock column is unchanged code in all four builds and its median spread
across them is 0.5 %:

build	ratio vs stock	worst cell	cells at or below 1.00×
995cd99 (before these commits)	1.01–2.13×	2.13×	0/43
+ blocked emission	0.72–1.79×	1.79×	10/43
+ threshold only	1.01–2.13×	2.13×	0/43
both (this branch)	0.72–1.78×	1.78×	27/43

The two compose: there is no cell where both together are worse than either alone. The worst cell is
64 × 24,576, which sits just above the caching bound and so is multi-CTA under every legal threshold
— no value of that constant can reach it.

2.13× here is worse than the 2.14× headline above only because this grid is wider: it adds
n = 17,408 / 20,480 / 21,504 / 24,576, which the earlier grid did not contain. The earlier number was
not wrong for its grid; this one covers more of the space.

Hardware risks a reviewer should weigh

These are properties of the code, not of the measurements, and only the first is new here.

• The ≥128 KiB filtered path costs 1.1–2.7×, measured on H100 and A100 (numbers).
  With num_rows > 32 and ≥128 KiB the op takes FilteredTopKRaggedTransform, whose per-row work is
  now det_select_row. GB10 offers 99 KiB and never executes that branch, so I rented the hardware:
  correctness holds on both parts, and the cost is worst at very long rows (n=65,536), where the row
  cannot be cached in shared memory on any current part. Sizing the request from the device rather
  than a 128 KB constant took n=40,000 from 2.41× to 1.74× on H100 and is included here. The affected
  regime is rows > 32 — large batch and prefill, not the c=1 decode shape.

• The inter-CTA barrier is a spin-wait under a non-cooperative launch. Residency is estimated
  host-side from cudaOccupancyMaxActiveBlocksPerMultiprocessor and capped with headroom. Concurrent
  kernels, MPS, or another stream can invalidate that estimate, and at occupancy 1 the reservation is
  one CTA globally rather than one per SM. This is inherited, but lowering RADIX_THRESHOLD to 16,384
  makes the cooperative path reachable more often, so this PR increases the exposure.

• RADIX_THRESHOLD is device-tuned. It was 16,384, which measurement showed was too low; this
  branch now ships 22,016. (Updated 2026-09-08 with a threshold sweep; the earlier text said only that no scalar value
  is right, which understated how much 16,384 costs.) Three builds differing only in this constant,
  three benchmark starts each, widths chosen so the routing actually flips between them. det µs, min
  of 3 starts, S = single-CTA select, M = multi-CTA cooperative radix:

  rows	n	16384	20480	22016	routing	multi-CTA costs
  64	17408	53.3	34.8	34.8	M/S/S	+53 %
  64	20480	57.4	38.8	38.8	M/S/S	+48 %
  64	21504	59.5	59.5	39.4	M/M/S	+51 %
  8	17408	22.6	18.5	18.5	M/S/S	+22 %
  1	17408	19.1	16.5	16.5	M/S/S	+16 %

  Controls hold: n = 16,384 (single-CTA under all three) and n = 24,576 / 32,768 (multi under all
  three) are flat across arms, so the effect appears only where routing changes. Every width in
  16,384 < n ≤ 22,016 was being sent to a path costing 16–53 % more, worst at 64 rows. 22,016 is
  the largest legal value: the select caches the row while fixed(4256) + 4n ≤ 101,376, i.e.
  n ≤ 24,280, so 24,576 would silently fall to the uncached path — which is very likely why raising
  it all the way back to 32,768 costs 60–100 % at n = 24,576–32,768 on 1–8 rows. Both statements
  hold: 32,768 is too high and 16,384 is too low. The correct value on another GPU is still
  unknown, since the bound is that device's shared-memory opt-in.

  This does not reach the 64 × 32,768 cell in the cost table above: n = 32,768 is multi-CTA under
  every legal threshold, so no value of this constant can move it.

• __launch_bounds__(kThreadsPerBlock, 2) is silently ignored on this part. nvcc reports "Value of
  threads per SM ... is out of range" for every instantiation: 1024 × 2 exceeds the 1,536 threads per SM
  this device reports. Pre-existing, and left alone because changing launch bounds needs its own
  measurement, but the occupancy the source asks for is not the one it gets.

Test plan

• New tests in tests/kernels/test_top_k_per_row.py: test_persistent_topk_deterministic (rows {1, 8, 64} × lengths {1k, 4k, 8k, 20k, 40k} × k {512, 2048} × {random, tie-heavy}: 6 calls bit-identical and equal to the exact reference), test_persistent_topk_all_equal (all keys equal → exactly [0, k) 20×), test_persistent_topk_pivot_ties (tie populations of 2047 … 16385), test_persistent_topk_narrow_value_range (every key in one coarse histogram bin, the [Bug]: persistent_topk silently drops top-k candidates when many values share a coarse histogram bin #51782 shape: no candidate may be dropped).
• The same shapes were run against a standalone build of these exact sources on a GB10 (sm_121): 210 / 210 pass; on the same inputs the unmodified kernel reproduces its own output in 0 / 210 cases.
• Correctness is verified on three architectures: sm_121 (GB10), sm_80 (A100 80GB) and sm_90 (H100 80GB). The last two were rented, with both arms built from source on the box and three starts each, because the num_rows > 32 filtered path needs ≥128 KiB of opt-in shared memory and GB10 offers 99 KiB — so that path cannot be exercised here at all. Blackwell and ROCm remain untested. No atomicAdd slot assignment remains on any path.

Test result

GB10 / sm_121, TP1, built from this branch's head:

• pytest tests/kernels/test_top_k_per_row.py -k persistent_topk: 221 passed, 26 skipped.
• Standalone harness over the determinism / exactness grid: 210 / 210. The unmodified kernel reproduces its own output on 0 / 210 of the same inputs.
• End to end, server-level A/B with three starts per arm: no measurable change in decode or TTFT (numbers here).
• Not from this PR, but seen while running the file on this box: all 51 cooperative_topk cases fail with cooperative_topk launch failed: invalid argument (cooperative_topk.cu:48). The backend is gated on SM90+, which sm_121 satisfies, but the cluster launch is rejected here. This PR does not touch that op.

Relates to #54521 — this PR does not close it. Measured end to end on GB10, this kernel alone leaves greedy decoding non-reproducible (330 disagreeing positions against a no-fix control of 333; all four patches we run together give 0). It is one necessary component of a set, not the fix; see the correction in the thread. Fixes #51782 (the candidate buffers whose overflow dropped keys no longer exist; the narrow-range test covers that shape). #53287 explores the same two defects with a different mechanism (wider coarse histogram, exact fallback on overflow, buffered paths kept); this PR removes the buffers instead and also fixes the output order. Related: on our GB10 stack it takes four patches together to make Qwen3.8-Flash-Next reproducible — this kernel, the FlashInfer CUTLASS MoE fused finalize (#54945, PR #54948), a FlashInfer autotune cache key that includes use_fused_finalize, and a PLE offload semaphore reset. The last is in no released vLLM and not on main (vllm/v1/ple_offload/ does not exist upstream; #53899 is open with conflicts), so this list is not reproducible from vLLM alone today. The align-mode block-size PRs #54076 / #53798 are also in that area; bisection thread in #53142; #54912 (QSA ring bound).

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[k3dani]

Independently validated on a single NVIDIA GB10 (sm_121a, aarch64) with RadixArk/Qwen3.8-Flash-Next-NVFP4, using our production-like vLLM configuration: prefix caching, chunked prefill, PIECEWISE CUDA graphs, MTP=2, FlashInfer 0.6.17, and 8K prefill chunks.

I built the standalone _C_det.so against our existing PyTorch 2.13 / CUDA 13 image and ran test_det.py: 0 failures. On the same test inputs, the stock persistent_topk was neither call-reproducible nor set-equivalent to the exact reference.

End-to-end A/B/C results:

• Stock persistent_topk: 0/4 prompts reproducible. Each prompt produced 10 distinct token-level top-20 logprob hashes across 10 identical requests.

• Our existing exact torch.topk workaround: reproducible under a fixed cache path.

• VLLM_QSA_DET_TOPK=1: equally reproducible under the same conditions.

Prefill throughput:

Prompt | Stock | Exact torch.topk | Deterministic kernel -- | -- | -- | -- 6,082 tokens | 2,246 tok/s | 1,952 tok/s | 2,253 tok/s 24,416 tokens | 1,943 tok/s | 1,756 tok/s | 1,932 tok/s

On these two clean long-prompt measurements, the deterministic kernel retained 99–100% of stock throughput, while the Python exact fallback retained only 87–90%.

The deterministic kernel and the exact fallback do not necessarily produce identical model outputs, because their selected-index ordering differs and sparse-attention accumulation is order-sensitive. We are therefore running our 50-item Hungarian KIE quality suite before production adoption. However, the kernel correctness, request-level reproducibility, and performance validation on GB10 were successful.

Standalone source tested: jschmied/qwen38-flash-next-gb10@0c5598782b33bbfc9acb46acd57b495ca0eb01b7.

Activation was verified from the server log:

QSADET active: .../_C_det.so

[jschmied]

Thanks for the independent run — the 99–100 % vs 87–90 % throughput split matches what the microbenchmark predicted.

On the ordering point: both selections return the same set; this kernel emits it in ascending index order, torch.topk in descending value order, and the sparse attention sums in output order, so the two can differ at the last ulp. Each is reproducible with itself; neither is "more correct". If your KIE suite shows a difference between them, that is a tie-break/summation-order effect, not a selection error — happy to see the numbers either way.

Our own before/after on the same kernel (TTFT 8k/30k and MTP decode, 3 starts each) follows here once the box is free.

[k3dani]

Details behind the numbers above (added after the 50-item suite finished)

Environment — identical on all three arms except the top-k selection:
vllm/vllm-openai:qwen38-flash-next@sha256:fc120ece0a388cc0aa1caad4a9f1cd92113484ab7ec2fd0efadd62585be05bf8
(vLLM 0.1.dev20073+g8e685d198, torch 2.13.0+cu130, FlashInfer 0.6.17), driver 580.173.02,
RadixArk/Qwen3.8-Flash-Next-NVFP4 @ 7b719225…, PLE table mmap-ed (blazux e655b7d layer).
Launch: --max-model-len 262144 --max-num-seqs 4 --gpu-memory-utilization 0.78 --enable-prefix-caching --enable-chunked-prefill --max-num-batched-tokens 8192 -cc.cudagraph_mode=PIECEWISE (12 splitting ops), --speculative-config '{"method":"mtp","num_speculative_tokens":2}', --kv-cache-dtype auto, --no-enable-flashinfer-autotune. The startup log confirms Mamba cache mode … 'align' and the FLASHINFER_CUTLASS NvFp4 MoE backend. The .so was built in-image with build_det.py (nvcc sm_121a, -DUSE_CUDA); test_det.py: 0 FAILS, every row stock identical x3=False and stock set==ref=False.

Probe — identical chat requests sent strictly sequentially (Running: 1 reqs throughout), temperature=0, top_logprobs=20; per generated token a sha256 of the top-20 (token, logprob) list, run hash over the sequence. Prompts of 3.2k–24.4k tokens (Hungarian document-extraction tasks).

arm	4 prompts × 10 requests, 48 tokens, thinking off	4 prompts × 5 requests, 512 tokens, thinking on
stock persistent_topk	0/4 — 10 distinct hashes per prompt, diverging at token 0	—
exact torch.topk (Python)	3/4 (see note)	4/4, incl. the 24.4k prompt
VLLM_QSA_DET_TOPK=1	3/4 (same prompt, same pattern)	4/4

Note on the 3/4: the one prompt that "failed" did so identically on both deterministic arms and only in its first request — it shares ~2.2k prefix tokens with the previous prompt, so request 1 was a partial prefix-cache hit and requests 2–10 full hits, and the two cache paths give different logits (all 46 tokens' top-20 lists; visible text unchanged). That is the align-resume path (#53798 / #54076, #54173), not this kernel; in a round where the same prompt ran in a different cache state it passed 8/8. Mentioned so it is not read as a regression of the PR.

What the kernel does not change (also measured on both deterministic arms): batch invariance. With 2 or 4 identical concurrent requests none matched the sequential hash (0/6, 0/12) and the requests differed from each other; a mixed batch was self-consistent (3/3) but ≠ sequential. Visible text identical in all cases. Expected on this model (VLLM_BATCH_INVARIANT is unavailable for GDN, #42960) — stated so nobody expects cross-batch reproducibility from this PR.

Decode — unchanged within noise on 512-token generations (e.g. 16.8–17.1 s exact vs 17.1 s det for the same prompt). The 10–24 % "warm request" gain we saw at 48 tokens is the residual prefill of the last partial block, not decode.

MoE (#54945) — on these shapes we saw no fused-finalize divergence at all (0 differences across 80 warm requests, thinking on and off) with the CUTLASS backend active. Shape-dependent, evidently; a data point for that issue, not a counter-claim.

Quality — 50-item Hungarian KIE suite, 3 runs per item, majority scored, with the deterministic kernel: 95/100, 0/50 unstable, all 150 requests finish=stop. References on the same corpus: stock kernel 97/100 with 13/50 unstable items; our exact torch.topk on the same image 96/100 (one run). The one-point gap is a single working-day-deadline item where the reasoning forks at a near-tie (2026-12-30 vs 2027-01-05); the other differing item scores 0 on both deterministic arms for a serialisation reason unrelated to the kernel. So: same stability, essentially stock speed, one tie landing differently on 50 items — we treat it as the candidate and will run the harder suites before switching.

Full artefacts (probe code, every raw JSON, notes):
https://github.com/k3net/docai-evals/tree/master/experiments/2026-09-03-qwen38-flash-next-det-topk-kernel-batch-invariance-gb10

[jschmied]

Thank you — that is the validation this PR needed, and the artefact repo makes it reproducible.

Two notes on your findings, both agreeing with yours:

• The 3/4 case (first request a partial prefix-cache hit, logits differ from the full-hit path, text unchanged) is the align-resume path: vllm#54076 / [Bugfix] Seed align-mode Mamba state_idx in Mamba blocks #53798 change the block-boundary seeding for hybrid models; with both applied on our box the partial-hit and cold paths agree. Independent of this kernel, as you say.
• Batch invariance: correct, nothing here changes it; the GDN path has no batch-invariant mode.

The MoE data point (no fused-finalize divergence on your shapes) is useful for #54945 — on our shapes it showed only in the decode step at M ≤ 52 tokens, never at M = 55, so it is shape-gated.

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Walkthrough

Changes

The persistent top-k implementation now uses deterministic radix selection for nontrivial rows. It applies index-ordered tie handling, direct multi-CTA placement, dynamic shared-memory sizing, filtered-row length clamping, and expanded reproducibility tests.

Persistent top-k determinism

Layer / File(s)	Summary
Deterministic selector and dispatch csrc/libtorch_stable/persistent_topk.cuh	Adds exact radix selection, canonicalizes signed zero, lowers RADIX_THRESHOLD, removes obsolete histogram paths, and updates filtered top-k to use deterministic selection.
Deterministic multi-CTA placement csrc/libtorch_stable/persistent_topk.cuh	Publishes per-CTA pivot counts and writes selected elements directly to final positions using CTA-prefix scans.
Launch sizing and fallback wiring csrc/libtorch_stable/topk.cu	Reads device limits per launch, accounts for static shared memory, validates tensor and geometry constraints, and routes low-memory launches through deterministic single-CTA selection.
Deterministic correctness coverage tests/kernels/test_top_k_per_row.py	Tests threshold transitions, reproducibility, ties, signed zero, short rows, clamped lengths, histogram boundaries, and narrow value ranges.

Estimated code review effort: 4 (Complex) | ~60 minutes

Merge Risk: 🔵 Low · up to a4e97

The kernel’s core selection behavior is covered, but the degenerate-row test can miss regressions in other rows and empty inputs can silently bypass the public API contract. Resolve these bounded issues before merge.

Sequence Diagram(s)

sequenceDiagram
  participant topk_launch
  participant PersistentTopKParams
  participant persistent_topk_kernel
  participant det_select_row
  participant output
  topk_launch->>topk_launch: read device limits and validate inputs
  topk_launch->>PersistentTopKParams: set det_smem_bytes and force_single_cta
  topk_launch->>persistent_topk_kernel: launch with active-width geometry
  persistent_topk_kernel->>det_select_row: select exact top-k indices
  det_select_row->>output: emit deterministic final positions

Loading

🚥 Pre-merge checks | ✅ 5

✅ Passed checks (5 passed)

Check name	Status	Explanation
Linked Issues check	✅ Passed	The changes address both linked issues [#54521] and [#51782] by making single-CTA and multi-CTA selection deterministic, enforcing ascending-index tie-breaking, removing candidate-buffer truncation, a…
Out of Scope Changes check	✅ Passed	The launcher updates, validation changes, fallback handling, threshold adjustment, and regression tests directly support deterministic and exact persistent_topk behavior. No unrelated code changes are…
Docstring Coverage	✅ Passed	Docstring coverage is 86.67% which is sufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 15 functions across 2 files. (1 skipped: 1 …
Title check	✅ Passed	The title clearly and concisely describes the main change: making the persistent_topk CUDA kernel deterministic.
Description check	✅ Passed	The description is directly related to the changeset and explains the determinism fix, selection behavior, launcher changes, performance considerations, and test coverage.

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Actionable comments posted: 2

🤖 Prompt for all review comments with AI agents

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Inline comments:
In `@csrc/libtorch_stable/topk.cu`:
- Around line 117-118: Update launch_persistent_topk so max_smem_per_block is
obtained for the active DeviceGuard-selected CUDA device rather than shared
across devices; either cache sharedMemPerBlockOptin per device or query it after
the guard, ensuring smem_size never exceeds the current device’s limit before
cudaFuncSetAttribute.

In `@tests/kernels/test_top_k_per_row.py`:
- Line 1347: Add 1024 to the top_k parameterization used by the deterministic
exactness matrix in the relevant test, and include a tie-heavy case for that
value so the dispatcher’s distinct 1024 instantiation is covered alongside 512
and 2048.

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[jschmied]

End-to-end numbers on GB10 (sm_121) for this PR's kernel, three server starts per arm, Qwen3.8-Flash-Next (QSA top-k on 8,192-row scores, ModelOpt NVFP4/FP8 checkpoint), vLLM preview build, MTP n=5, prefix caching on:

	stock (a / b / c)	this PR (a / b / c)
TTFT 7.5k tokens, median of 3	3.10 / 3.29 / 3.10 s	3.12 / 3.35 / 3.12 s
TTFT 29k tokens, median of 3	11.24 / 11.55 / 11.26 s	11.22 / 11.62 / 11.27 s
8-turn agent loop, s per turn	2.70 / 2.68 / 2.68	2.69 / 2.54 / 2.66

Every pair is inside the start-to-start band, i.e. no measurable TTFT or per-turn cost at the server level. A third arm that forces the exact selection through torch.topk produced byte-for-byte the same 8-turn run as the PR's kernel on all six starts (166 tokens, 65 drafts, 111 accepted), so the selected set is the exact one, and it is stable across restarts; the stock arm's runs differ from each other and from those (208–224 tokens).

[jschmied]

Two commits pushed.

c564e5c — the host guard rejected short rows. The chunk_size >= TopK check I added with the
kernel is unconditional, but only the cooperative large path (max_seq_len > RADIX_THRESHOLD) ranks
the final candidates inside CTA 0's chunk buffer and needs it. Rows at or below the threshold take
the single-CTA select, or the trivial seq_len <= TopK case, and never touch that buffer.

That shape is not hypothetical: the block-level QSA indexer calls persistent_topk with
TopK = token_topk / compress_ratio = 512 over a few hundred blocks at warm-up, so on a build that
takes that path the server died at start with

persistent_topk: chunk_size 256 smaller than TopK 512

The guard is now conditional on the path, and the message names it.

New regression test test_persistent_topk_short_rows: rows of 256–2048 at TopK 512/1024/2048,
33 cases. The exactness matrix skipped every one of these, because it required top_k < seq_len.
The reference now pads the unused slots with -1, which is what the kernel writes there.

On a GB10 (sm_121, TP1, torch 2.13 / CUDA 13), this PR's kernel built standalone and driven by the
PR's own test file:

	short-row cases	whole persistent_topk_ selection
with c564e5c	33 passed	134 passed, 26 skipped
without it	24 failed, 9 passed	—

The 9 that pass without the fix are the seq_len == top_k cells, where chunk_size happens to
satisfy the old check.

afd9281 — the review round from 03 Sep. Per-call device properties (the static cache was shared
across devices, and the dynamic-smem cap depends on the device the launch runs on) and k=1024 in
the exactness matrix. I committed this locally on the 3rd and reported it here, but never pushed it;
it is on the branch now. Apologies to anyone who read the diff in between.

pre-run-check fails on the label policy, not on the code; format checks (clang-format, ruff) are
clean locally.

AI assistance was used for this change; every line was reviewed by me before pushing.

[jschmied]

Sorry for the slow reply. On the substance I think you are right, and our own data supports your
position rather than mine.

The defect this PR fixes is unreachable on the traffic we censused. Of 6,192 rows that actually
performed a selection, 0 had any tie at the k-th value (93 % of rows had fewer visible blocks
than k, so selection was a no-op). Stated with its bound, because it matters: that census was at
16k context over two prompts, so it says nothing about the long-context regime where
#51782 is now seeing trouble. Within that
bound, what this PR buys is kernel correctness under ties rather than end-to-end determinism — our
framing to own, and it argues against changing a default.

We have effectively been running your design for a week. Our deployment carries the
deterministic kernel out-of-tree behind an env flag (VLLM_QSA_DET_TOPK), opt-in, default off. That
is the shape you are proposing.

One more argument against defaulting it, from this week. The deterministic path wants the row
resident in shared memory. On GB10 (sharedMemPerBlockOptin = 101,376 B) that request exceeded the
device at ~100k context and hard-failed:

persistent_topk_det: dynamic smem 98080 exceeds 97120 (optin 101376 - static 4256)

The failure to clamp is in our out-of-tree wrapper and is ours to fix — but the appetite is the
deterministic algorithm's, and a low-shared-memory device cannot always satisfy it. That is a reason
for opt-in, not for a default.

Yes, we can test #55872 here and will report back. It is pure Python and it touches our exact
path (models/qwen4_exp/nvidia/indexer_qsa.py, ops/qsa_indexer.py), so it is straightforward on
one GB10, sm_121, TP1, Qwen3.8-Flash-Next NVFP4.

One scoping note that may matter for where the backend hooks in: on GB10 the stock path is not
persistent_topk for every row. Leaving it for top_k_per_row_decode needs three conditions
together — row length above RADIX_THRESHOLD, the cooperative launch oversubscribing, and
sharedMemPerBlockOptin < 128 KiB. GB10 always meets the third, so short rows and long rows here run
different kernels. A backend that wraps only the persistent_topk selection would cover the short-row
case on this hardware and miss the long-row one.

[jschmied]

Ran #55872 here as promised. It does not start on GB10 (sm_121). Details below, including what I
ruled out, because the error is not the one I first assumed.

Setup: clone of a dev524 venv with your PR applied — all 7 runtime files patched clean, only the
tests/ file skipped. FlashInfer 0.6.18.post1. Qwen3.8-Flash-Next NVFP4, --dsa-topk-backend flashinfer, and I set VLLM_QSA_DET_TOPK=0 so our own out-of-tree deterministic kernel could not
mask yours — your hook at qsa_indexer.py returns before it, so leaving ours on would have made the
control arm not-native.

The native arm is fine: 8/12 on a 12-prompt exact-copy probe, matching our unpatched baseline
exactly, so the patch itself is not disturbing the default path.

The flashinfer arm fails at engine init. The flag parses — the config echo shows
dsa_topk_backend='flashinfer' — and then:

flashinfer/topk.py:329 in radix_topk_ragged_transform
  -> csrc/topk.cu:269 in radix_topk_ragged_transform
RuntimeError: Check failed: (status == cudaSuccess) is false:
  TopKRaggedTransform failed with error code operation not supported
Engine core initialization failed.

What this is not

I assumed a missing kernel image and that turned out to be wrong, so I checked:

• "operation not supported" is cudaErrorNotSupported (801), not
  cudaErrorNoKernelImageForDevice (209). So it is not an absent cubin.
• topk.so in flashinfer-jit-cache 0.6.18.post1 carries ELF for
  sm_80 sm_89 sm_90a sm_100a sm_103a sm_110a sm_120 and no PTX. sm_120 should load on sm_121 by
  minor-version forward compatibility, consistent with 209 not being what we got.
• The obvious device capabilities are all present: cudaDevAttrCooperativeLaunch 1,
  cudaDevAttrClusterLaunch 1, cudaDevAttrCooperativeMultiDeviceLaunch 1.

The lead I would follow

That leaves a launch-resource request the device cannot satisfy, and GB10's headline number is small:
cudaDevAttrMaxSharedMemoryPerBlockOptin = 101,376 B, against ~227 KiB on H100-class parts.

I say that with some confidence because we hit exactly this ceiling in our own top-k kernel yesterday,
on this device, with a near-miss:

dynamic smem 98080 exceeds 97120 (optin 101376 - static 4256)

960 bytes over. If FlashInfer's radix top-k sizes its shared-memory request from a datacenter
assumption, sm_121 is the first arch where it does not fit, and a 100 KiB ceiling would explain an
801 rather than a 209.

Which I think supports your position, not mine

This makes the opt-in argument stronger. A GB10 user on your backend gets engine-init failure, and
one on a deterministic-by-default kernel would get the hard failure we just found in ours. Neither is
acceptable as a default; both are fine as opt-in with a capability check. If it helps, a guard on
sharedMemPerBlockOptin (or a documented minimum) would turn this from a crash into a clean
"backend unavailable on this device".

Happy to re-run with any instrumentation you want — one GB10, sm_121, TP1, and no stake in the
outcome. If you can print the requested shared-memory size before the launch, that would confirm or
kill the hypothesis in one run.

[k3dani]

Independent GB10 numbers: the deterministic kernel costs nothing — it is 21–28% faster than the exact-topk workaround

Second data point from a DGX Spark (GB10, sm_121, ARM64), this time on the official
vllm/vllm-openai:v0.29.0 image (VLLM_BUILD_COMMIT=98dff2a81d74) rather than the preview build in
our 3 September comment above. The kernel is compiled into the image for sm_121a and its activation is
proven in the log (QSADET active: …/_C_det.so), not just by an env var.

Both arms: same machine, same checkpoint (RadixArk/Qwen3.8-Flash-Next-NVFP4, snapshot
7b71922…), same flags (--max-model-len 262144 --max-num-seqs 4 --gpu-memory-utilization 0.78 --enable-prefix-caching --enable-chunked-prefill --max-num-batched-tokens 8192, PIECEWISE cudagraphs,
MTP=2, --kv-cache-dtype auto), temperature=0. Cold prefill at each step (unique filler seed per
step, vllm:prefix_cache_hits_total flat).

prompt tokens	exact torch.topk	this PR's kernel	speedup
8 024	1 736 tok/s	2 097	+21%
16 019	1 825	2 282	+25%
24 027	1 866	2 293	+23%
32 022	1 877	2 346	+25%
48 025	1 884	2 346	+25%
64 028	1 815	2 315	+28%

Host memory stays on a flat plateau on both arms (before-step readings within 15–45 MB of each other
across the sweep; the only larger move is a 425 MB drop after arm A's 64K step); no preemption, no
OOM, no worker restart in either log. The sweep stops at 64k, so it says nothing about the ~100k
regime where the shared-memory limit noted above bites — the det arm here is the same out-of-tree
wrapper (jschmied/qwen38-flash-next-gb10 @ e0ef69d).

Determinism is unchanged: on our 4-item greedy probe (10 repeats each, full per-token top-20 logprob
hash) both arms give 3/4 stable. The one item that differs does so identically on both arms — we
traced that to cross-request prefix-cache reuse, unrelated to top-k; details in our report on #54076.

So on this hardware the deterministic kernel is not a trade-off at all: it replaces a workaround that
costs 21–28 % of prefill throughput, at the same determinism.

Raw output and tooling: https://github.com/k3net/docai-evals/tree/b1f14a36c5bcc02cf2cd65705031e676fa9cb73f/experiments/2026-09-12-qwen38-flash-next-prefix-cache-cross-request-gb10
(the sweep is results/round3-{A,B}-memoria.json, the probes results/round3-{A,B}-szonda-48tok.json)

[MaCoredroid]

At 7cfd04a3 (kernel sources unchanged at a7188289e; only the test file changed), a standalone GB10 harness using the unmodified PR kernel header and a transcribed launcher exercised the low-shared-memory overflow fallback (48 SMs, 101,376 B opt-in shared memory). This ran alongside another workload.
For contiguous float32 rows with stride=length, rows {1,4}, k {512,1024,2048}, and random, tie-heavy and all-equal inputs, widths {355588,400000,474112} logged force_single_cta=1. The launch parameters and source select the uncached det_select_row path. All 324 fallback launches matched a stable value-descending/index-ascending reference, with selected indices sorted ascending, and were identical across six repeats per case; no output poison remained. Width 355584 added 108 passing cooperative-control launches; 474116 produced 18 expected pre-launch >64-CTA rejections.
Harness, source hashes and logs: https://github.com/MaCoredroid/Lumo_FlyWheel/tree/1536dae35436ec11de78367cccbf14e5dd36950c/results/upstream/55122. This supports exactness and repeatability for these cases on one device; it does not validate torch/vLLM operator registration, CUDA graphs, other streams or broader determinism. No performance claim.

These measurements exercise the stock fallback conditions you described, using this PR's force_single_cta/uncached det_select_row path at our tested widths.

[mergify]

This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @jschmied.

https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/working-with-forks/syncing-a-fork

[jschmied]

Rebased onto b6e2aa748b; 15 commits, conflict-free. The only conflict was in
tests/kernels/test_top_k_per_row.py against #56464 and was purely additive on both sides — no
overlapping names, both test sets kept. Neither kernel source moved upstream: persistent_topk.cuh
and topk.cu diff byte-for-byte identically to before the rebase, and the five commits that
disappeared were earlier Merge branch 'main' syncs.

For anyone reading after #56464: persistent_topk is still live as the persistent backend in the
new indexer_topk.py dispatcher, so this fix now applies to a path selected explicitly.

@MaCoredroid — thank you, and sorry for the slow acknowledgement. Driving force_single_cta /
uncached det_select_row directly at 48 SMs and 101,376 B opt-in shared memory is the case we could
argue for but not demonstrate; 324 fallback launches matching a value-descending / index-ascending
reference across six repeats each, plus the cooperative-control launches at 355584 and the expected

64-CTA rejections at 474116, says more about the fallback than anything in the PR body. Publishing
the harness and source hashes is what makes it checkable, and your scope note is right — one device,
kernel level, nothing about operator registration, CUDA graphs, other streams or performance.

With @k3dani's serving-level run that is two independent GB10 confirmations from different angles.