[ROCm][Perf] W4A16: keep skinny GEMM zero-points packed 4-bit - #54965
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Ran on my 9070 XT w/ 16GB of VRAM, results are inline with your table and all unit tests passed |
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📝 SummarySummary by CodeRabbit
WalkthroughW4A16 asymmetric quantization now uses packed int32 zero points. Each word stores eight row nibbles. ROCm and Triton kernels decode the packed format, host validation enforces its shape and dtype, and RDNA tests cover packing and rejection of unpacked inputs. ChangesPacked zero-point integration
Estimated code review effort: 3 (Moderate) | ~20 minutes Merge Risk: 🟡 Moderate · up to Packed asymmetric zero points reduce memory traffic, but asymmetric layers whose output size is not divisible by eight can be selected and then fail at runtime rather than using a supported implementation. Add selection-time validation before merging. Sequence Diagram(s)sequenceDiagram
participant WeightLoader
participant GEMMWrapper
participant QuantizationKernel
WeightLoader->>GEMMWrapper: provide packed int32 zero points
GEMMWrapper->>QuantizationKernel: validate [N/8, K/G] layout
QuantizationKernel->>QuantizationKernel: extract row nibble
QuantizationKernel->>QuantizationKernel: apply zero-point dequantization
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✅ Passed checks (4 passed)
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Inline comments:
In `@vllm/model_executor/kernels/linear/mixed_precision/rdna_hybrid_w4a16.py`:
- Line 532: Update can_implement to reject asymmetric configurations when
partition_weight_shape[1] is not divisible by eight, while preserving existing
acceptance behavior for symmetric configurations and valid asymmetric
dimensions.
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RDNAHybridW4A16LinearKernel expanded the asymmetric zero-points to the
activation dtype at load time, so wvSplitK_int4_g read an [N, K/G] fp16/bf16
tensor. Those values only ever span 0..15, so that spends 2 bytes on 4 bits
of information.
Keep them in the packed form the checkpoint already ships: [N/8, K/G] int32,
row n's nibble at word[n/8] bits 4*(n%8). process_weights_after_loading now
passes the loaded tensor straight through instead of unpacking and casting
it, and both consumers unpack the nibble inline - a shift and a mask in the
HIP kernel (zp_nibble) and in the Triton prefill kernel. Dequant is
unchanged: (nibble - zp_raw) * scale.
Two effects, on the two paths:
- Decode (HIP skinny, memory-bound): zero-point traffic drops 4x, which is
2.2% of weight-side DRAM bytes at group_size=128, rising to 7.5% at 32.
- Prefill (Triton): the per-group metadata load is a gather strided by
num_groups, so its cost is distinct cache lines touched rather than bytes.
Eight N-rows now share one word, so a BLOCK_N=64 tile touches 8 lines
where it previously touched 32.
Benchmarked on AMD Strix Halo (gfx1151, 40 CU, LPDDR5X), ROCm 7.15,
torch 2.12. input-len 128, output-len 128, num-prompts 5, 3 reps per arm,
arms interleaved:
RedHatAI/Qwen3-8B-quantized.w4a16 (asymmetric, group_size 128):
Median TPOT: 24.136 ms -> 23.776 ms (-1.49%)
Median TTFT: 129.36 ms -> 121.40 ms (-6.15%)
RedHatAI/Qwen3-4B-quantized.w4a16 (symmetric, no zero-points; control):
Median TPOT: 13.499 ms -> 13.519 ms (+0.15%)
Median TTFT: 66.90 ms -> 66.74 ms (-0.23%)
The subject's TPOT rep ranges do not overlap ([23.753, 23.784] after vs
[24.136, 24.564] before) while the control's fully overlap, so the decode
result is separated from run-to-run noise. The control moves the wrong way
by a tenth of a percent, as it must: symmetric layers carry no zero-point
tensor and take an unmodified path.
Changes:
- The op's zero-point argument changes format. wvSplitK_int4_g is only
reachable through this kernel, so no other caller has to be migrated, but
the old act-dtype tensor is 2D with compatible extents and would be
silently misread as packed words rather than rejected - hence the explicit
int32/uint32 dtype check, covered by a regression test.
- zp_nibble keeps signed parameters and the shift/mask spelling on purpose.
Switching to unsigned parameters and row/8, row%8 is arithmetically
equivalent but pushes the (A_CHUNK=32, UNRL=8) instantiation from 239 to
256 VGPRs plus 68 bytes of scratch.
- The symmetric path is untouched: it has no zero-point tensor at all.
Every intermediate (nibble 0..15, zero-point 0..15, difference -15..15) is
exactly representable in fp16 and bf16, so the change is bit-identical.
Greedy decode over 6 fixed prompts produces byte-identical text and token
ids on both arms, for both models above.
Tested:
pytest tests/kernels/quantization/test_rdna_hybrid_w4a16.py
84 passed - fp16/bf16 x group_size 32/64/128 x symmetric/asymmetric,
across both the M<=5 HIP decode path and the Triton prefill path
pytest tests/kernels/quantization/{test_rocm_compressed_tensors_w4a16,
test_w4a16_kernel_selection,test_triton_w4a16}.py
22 passed
pre-commit run --hook-stage manual on the changed files: all passed
AI assistance was used for this change.
Co-authored-by: Claude
Signed-off-by: Matthias Gehre <matthias.gehre@amd.com>
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✅ Queued 2 failed job(s) for retry in Buildkite AMD CI #12762. |
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✅ Triggered Buildkite CI #87918 for commit |
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✅ Queued 3 failed job(s) for retry in Buildkite CI #87918. |
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✅ Triggered Buildkite CI #88301 for commit |
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/ci retry |
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✅ Queued 2 failed job(s) for retry in Buildkite CI #88301. |
…roject#54965) Signed-off-by: Matthias Gehre <matthias.gehre@amd.com>
…roject#54965) Signed-off-by: Matthias Gehre <matthias.gehre@amd.com>
Purpose
RDNAHybridW4A16LinearKernelexpanded the asymmetric zero-points to theactivation dtype at load time (e.g. bf16 instead of int4), costing 4x the DRAM traffic.
This PR keeps them in the packed form (8x int4 inside an int32).
Performance
gemma-4-31B-it-AWQ-4bit uses
group_size=32and thus is more affected; in particular, the different layout moves more elements into a single cache line, which helps with cache trashing.Duplicate-work check
Searched open PRs for
wvSplitK_int4,rdna_hybrid_w4a16, andW4A16 zero point ROCm. No duplicate. Two open PRs are adjacent but distinct:Ignore redundant qzeros in symmetric RDNAHybridW4A16) edits thesame
if c.zero_points:block, but handles the symmetric GPTQ pathdropping redundant
qzeros. Orthogonal to this change, which is about theasymmetric zero-point memory layout. Whichever lands second needs a trivial
rebase.
W4A16: magic-bias dequant + scale hoist for gfx90a) changestriton_w4a16.py, a different kernel; it does not touch zero-point storage.Test Result
Byte-identical text and token_ids on both models before and after this PR.
AI assistance
AI assistance (Claude) was used for this change. The commit carries a
Co-authored-by: Claudetrailer. The submitting human has reviewed everychanged line and ran the tests reported above.