[Bugfix] Route FP8 MoE + LoRA to Marlin (W8A16) so MoE-LoRA kernels get unquantized activations

[waynehacking8]

Purpose

Fixes the remaining actionable part of #45101: make FP8 MoE + --enable-lora actually work, instead of crashing (today) or failing fast (#45130).

Root cause (matches the analysis in #45130 and my writeup on the issue): with an FP8 base MoE, the auto-selected w8a8 backends (e.g. TritonExperts) quantize activations to fp8 before the experts run, so the Triton MoE-LoRA shrink kernel receives fp8 x and crashes on the mixed fp8 × bf16 tl.dot — AssertionError: Unsupported lhs dtype fp8e4nv (Triton permits fp8 dot operands only when both sides are fp8). Arch-independent.

Fix: in select_fp8_moe_backend, when LoRA is enabled, route to the Marlin (W8A16) backend — activations stay in the original dtype and MarlinExperts already mixes in LoRAExpertsMixin, so the combination works. This mirrors the existing LoRA special case in the unquantized oracle (oracle/unquantized.py). Explicit --moe-backend / env overrides are still honored and fail with a clear reason via is_supported_config if incompatible.

Why this is not duplicating an existing PR

• [Bugfix][LoRA] Fail fast on FP8 MoE + LoRA instead of cryptic Triton crash #45130 adds a fail-fast error for this combination (LoRA mixin layer); it does not make the combination work. This PR is complementary — with both merged, the guard remains a safety net for any path that still feeds fp8 activations to LoRA kernels.
• Add support for LoRA with NVFP4 MoE models #34421 targets LoRA with NVFP4 MoE models (different quant scheme and code path).
• Searched open PRs for 45101, fp8 moe lora marlin — no other PR addresses backend selection for FP8+LoRA.

Test Plan

• New unit test tests/kernels/moe/test_fp8_backend_selection.py (block-fp8 and per-tensor fp8 schemes → MARLIN when is_lora_enabled).
• End-to-end on the issue's hardware class — RTX PRO 6000 Blackwell (SM 12.0), Qwen/Qwen3.6-35B-A3B-FP8 (block-fp8 [128,128], E=256), enable_lora=True, max_lora_rank=64.

Test Result

• pytest tests/kernels/moe/test_fp8_backend_selection.py → 2 passed
• pre-commit (incl. mypy-3.12 --hook-stage manual) → passed on changed files
• Before (main): Using TRITON Fp8 MoE backend → profiling forward crashes: AssertionError: Unsupported lhs dtype fp8e4nv → Engine core initialization failed (exact crash from [Bug]: FP8 MoE on SM120 (RTX PRO 6000 Blackwell) crashes in Triton fused_moe: AssertionError "Unsupported lhs dtype fp8e4nv"; VLLM_MOE_FORCE_MARLIN=1 not honored #45101)
• After (this PR): LoRA is enabled with an FP8 MoE: selecting the MARLIN (W8A16) backend … → engine initializes, coherent generation: The capital of France is → ' Paris, a city renowned for its iconic landmarks such as the Eiffel Tower,'

AI assistance disclosure

AI assistance (Claude Code) was used for analysis and drafting; I reviewed every changed line, ran the tests above, and validated end-to-end on real SM120 hardware.

Generated with Claude Code

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[waynehacking8]

Design note on scope (prompted by an offline review question — being explicit about what this PR is and isn't):

This PR is an availability fix at the selection layer, not the root fix. The root problem is that the Triton MoE-LoRA shrink consumes whatever activations the base path produces, and with w8a8 backends that's fp8 — and the bf16 LoRA-adapter dot can't take it.

The root fix is actually within reach in-tree: vLLM already has an fp8 MoE-LoRA kernel family (lora/ops/triton_ops/fused_moe_lora_fp8_op.py, fp8_kernel_utils.py — dequant-in-kernel via a_scale/b_scale), currently serving the fp8-quantized-adapter feature. The MoE LoRA dispatch in punica_gpu.py:add_lora_w13/add_lora_w2 hardcodes use_fp8_w8a8=False, and the LoRAExpertsMixin hooks don't thread a1q_scale through. Plumbing the activation scale into the hooks and dispatching to an fp8-input shrink variant would let FP8 MoE + LoRA keep the w8a8 base path (better large-batch throughput than the Marlin W8A16 route this PR selects).

Why I'd still merge this PR first:

• It makes the combination work today with an 8-line change that mirrors the existing LoRA precedent in oracle/unquantized.py, and converts a crash into a correct serving path.
• The kernel-level fix is a larger, independent change (punica API + dispatch + numerics validation), and the two compose cleanly: once fp8-activation LoRA kernels land, the Marlin branch added here can simply be deleted.

I'm happy to do that follow-up (I have SM120 + H100-class hardware for validation) — but flagging it here first in case the LoRA owners prefer a different design or want to take it.

[waynehacking8]

Closing in favor of #42120, which fixes this at the root: it threads the original unquantized hidden states into the MoE-LoRA shrink kernel (via MoELoRAContext.original_hidden_states), so the default Triton w8a8 FP8 MoE+LoRA path works correctly without escaping to Marlin W8A16 — keeping the higher-throughput path and also fixing the base-model corruption (#42008).

I validated #42120 on RTX PRO 6000 (SM120) and confirmed it resolves the same Unsupported lhs dtype fp8e4nv crash with byte-identical no-LoRA output, and my own design note here noted the Marlin reroute could be deleted once a root fix lands. That fix is #42120. Thanks!