[ROCm][DSv3.2] Adopt new paged-MQA-logits API + cached logits buffer with defensive padding#40643
Conversation
On gfx950 (MI355X) the aiter gluon preshuffle kernel `_gluon_deepgemm_fp8_paged_mqa_logits_preshuffle[_varctx]` (ROCm/aiter main, pre-vllm-project#2866) contains unmasked `buffer_store`s that can overshoot the logical row of `OutLogits_buffer` by up to ChunkKPerStage=128 float32 elements when `context_length == max_model_len` (because `split_context_length` is rounded up to a `KVBlockSize` multiple). This manifests as an intermittent HIP Memory Access Fault during DeepSeek V3.2 MTP speculative decode; the heisenbug quality comes from HIP's caching-allocator layout jitter relative to 2MiB hugepage boundaries. This change does two things: 1. Adopts the newer fused `deepgemm_fp8_paged_mqa_logits` API (and preshuffle path for block_size == 64) when the aiter build exposes it and `block_size > 1`, caching the output buffer across the 61 decode layers so we save a `torch.full(-inf)` per layer. The legacy `_stage1` + `out_qk.sum(dim=0)` path is preserved for block_size == 1 and older aiter builds. 2. Over-allocates the cached logits buffer by `_PAGED_LOGITS_ROW_PADDING = 256` float32 columns as defense-in- depth against the aiter OOB write, returning an `(rows, cols)`-shaped view with `stride(0) = cols + 256, stride(1) = 1`. The downstream `top_k_per_row_decode` consumer already threads `logits.stride(0)` / `logits.stride(1)` explicitly, so the widened row stride is transparent. Once aiter#2866 is merged and released the padding can be reduced to 0 with zero functional change. On MI355X with MTP=1, this eliminates the MAF at c=4 (bfloat16 4-way speculation) across 20/20 probe runs (the G6 vLLM-side probe that over-allocates logits by +1 row was the direct inspiration for the defense-in-depth approach adopted here). Cross-ref: ROCm/aiter#2866 (in-kernel fix). Signed-off-by: Martin Hartikainen <mahartik@amd.com>
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Code Review
This pull request introduces a padded output buffer for the paged MQA-logits kernel to mitigate out-of-bounds writes on ROCm and adds support for the fused deepgemm_fp8_paged_mqa_logits API. Feedback was provided to optimize the buffer caching mechanism by allowing reuse when the cached buffer is larger than requested, which prevents unnecessary reallocations while maintaining correct output dimensions for downstream operations.
| if ( | ||
| _cached_paged_logits is not None | ||
| and _cached_paged_logits.shape[0] == rows | ||
| and _cached_paged_logits.shape[1] == padded_cols | ||
| and _cached_paged_logits.device == device | ||
| ): | ||
| return _cached_paged_logits[:, :cols] | ||
| _cached_paged_logits = torch.full( | ||
| (rows, padded_cols), float("-inf"), device=device, dtype=torch.float32 | ||
| ) | ||
| return _cached_paged_logits[:, :cols] |
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The current caching logic for _cached_paged_logits reallocates the buffer whenever the number of rows (batch size * next_n) changes, including when it decreases. In dynamic scheduling scenarios common in vLLM, this leads to frequent VRAM reallocations and torch.full calls, which can degrade performance and increase memory fragmentation.
Additionally, the function returns _cached_paged_logits[:, :cols]. If the reallocation logic is improved to allow reusing a larger buffer (using >= rows), this slice would return more rows than currently requested. Since downstream operations like top_k_per_row_decode rely on logits.shape[0] to determine the number of rows to process, this could cause out-of-bounds reads on other metadata tensors like seq_lens if the buffer is larger than the current batch.
It is recommended to allow reuse when the buffer is large enough and to return a strictly sized view. Note that this assumes the kernel or downstream operations handle masking of stale data within the (rows, cols) area, which seems to be the case given the existing reuse logic.
| if ( | |
| _cached_paged_logits is not None | |
| and _cached_paged_logits.shape[0] == rows | |
| and _cached_paged_logits.shape[1] == padded_cols | |
| and _cached_paged_logits.device == device | |
| ): | |
| return _cached_paged_logits[:, :cols] | |
| _cached_paged_logits = torch.full( | |
| (rows, padded_cols), float("-inf"), device=device, dtype=torch.float32 | |
| ) | |
| return _cached_paged_logits[:, :cols] | |
| if ( | |
| _cached_paged_logits is not None | |
| and _cached_paged_logits.shape[0] >= rows | |
| and _cached_paged_logits.shape[1] == padded_cols | |
| and _cached_paged_logits.device == device | |
| ): | |
| return _cached_paged_logits[:rows, :cols] | |
| _cached_paged_logits = torch.full( | |
| (rows, padded_cols), float("-inf"), device=device, dtype=torch.float32 | |
| ) | |
| return _cached_paged_logits[:rows, :cols] |
The +256 col padding on _cached_paged_logits empirically eliminates a 2 MiB-aligned intermittent HIP MAF on MI355X / DSv3.2 MTP decode (20/20 sweep, zero faults). The earlier narrative attributed causation to an unmasked buffer_store in the aiter preshuffle kernel, but that op lowers to 'buffer_store ... offen' whose V# descriptor already does hardware bounds checking on gfx950 -- an overshoot there is dropped, not faulted. The most likely mechanism is an allocator-layout shift: the padding moves _cached_paged_logits away from a hugepage boundary where an adjacent kernel (quite possibly a PyTorch Inductor-generated 'triton_poi_fused_*' using global_store) writes into. This commit only rewords the module-level comment above _PAGED_LOGITS_ROW_PADDING and the docstring of _get_paged_logits_buffer to match that empirical story. No behavioural change.
maeehart
changed the title
Blocker: follow-up MAF reproduction on
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The AITER gluon preshuffle kernel (_gluon_deepgemm_fp8_paged_mqa_logits_ preshuffle) performs unmasked buffer_store writes up to ~190 float32 elements past context_length in each logits row when block_size=64. With the previous exact-size allocation those writes corrupt the logits of the adjacent row, causing wrong top-k selection and degenerate output. Fix: introduce _get_paged_logits_buffer that allocates (rows, cols + _PAGED_LOGITS_COL_PADDING) where _PAGED_LOGITS_COL_PADDING=256. The returned tensor is contiguous with stride(0)=cols+256, stride(1)=1. The only consumer, top_k_per_row_decode, already takes logits.stride(0) and logits.stride(1) as explicit arguments and bounds iteration by seq_lens, so the wider row stride is fully transparent. A fresh allocation is used on every call (rather than caching) so that each HIP graph bucket retains its own stable tensor pointer; caching a shared global that gets reallocated for a larger batch bucket would leave earlier-captured graphs with dangling pointers on replay. Also fixes a minor correctness issue: the previous code passed device="cuda" (always GPU 0) instead of q_fp8.device, which is wrong for TP ranks > 0 in tensor-parallel configurations. Validated: GSM8K 5-shot flexible-extract 0.9416 on TP4 with HIP graphs and block_size=64 (reference fork: 0.9409). Related: vllm-project#40643 (maeehart's companion PR: adopts the same padding with buffer caching and investigates the root-cause kernel; currently draft pending further MAF repro at num_speculative_tokens=2). Co-authored-by: Markus Hartikainen <maeehart@users.noreply.github.com>
The AITER gluon preshuffle kernel (_gluon_deepgemm_fp8_paged_mqa_logits_ preshuffle) performs unmasked buffer_store writes up to ~190 float32 elements past context_length in each logits row when block_size=64. With the previous exact-size allocation those stores corrupt the logits of the adjacent row, causing wrong top-k selection and degenerate output. Fix: introduce _get_paged_logits_buffer that allocates (rows, cols + _PAGED_LOGITS_COL_PADDING) where _PAGED_LOGITS_COL_PADDING=256. A non-contiguous [:rows, :cols] slice is intentionally avoided: deepgemm_fp8_paged_mqa_logits assumes contiguous output and would compute incorrect row offsets from a non-contiguous tensor. The full contiguous allocation ensures stride(0) = cols + 256 consistently; the padding columns absorb the OOB writes. top_k_per_row_decode takes logits.stride(0) and logits.stride(1) as explicit arguments and bounds iteration by seq_lens, so the extra columns are never read. A fresh allocation per call (no global cache) ensures each HIP graph bucket owns its own stable tensor pointer; a shared global reallocated for a larger bucket would leave earlier-captured graphs with dangling pointers on replay. Also fixes device="cuda" -> q_fp8.device so TP ranks > 0 allocate on the correct GPU. Validated: GSM8K 5-shot flexible-extract 0.9416 on TP4 with HIP graphs and block_size=64 (reference fork: 0.9409). Related: vllm-project#40643 (maeehart: same padding with caching, draft pending MAF investigation at num_speculative_tokens=2). Co-authored-by: Markus Hartikainen <mahartik@amd.com>
The AITER gluon preshuffle kernel (_gluon_deepgemm_fp8_paged_mqa_logits_ preshuffle) performs unmasked buffer_store writes up to ~190 float32 elements past context_length in each logits row when block_size=64. With the previous exact-size allocation those stores corrupt the logits of the adjacent row, causing wrong top-k selection and degenerate output. Fix: introduce _get_paged_logits_buffer that allocates (rows, cols + _PAGED_LOGITS_COL_PADDING) where _PAGED_LOGITS_COL_PADDING=256. A non-contiguous [:rows, :cols] slice is intentionally avoided: deepgemm_fp8_paged_mqa_logits assumes contiguous output and would compute incorrect row offsets from a non-contiguous tensor. The full contiguous allocation ensures stride(0) = cols + 256 consistently; the padding columns absorb the OOB writes. top_k_per_row_decode takes logits.stride(0) and logits.stride(1) as explicit arguments and bounds iteration by seq_lens, so the extra columns are never read. A fresh allocation per call (no global cache) ensures each HIP graph bucket owns its own stable tensor pointer; a shared global reallocated for a larger bucket would leave earlier-captured graphs with dangling pointers on replay. Also fixes device="cuda" -> q_fp8.device so TP ranks > 0 allocate on the correct GPU. Validated: GSM8K 5-shot flexible-extract 0.9416 on TP4 with HIP graphs and block_size=64 (reference fork: 0.9409). Related: vllm-project#40643 (maeehart: same padding with caching, draft pending MAF investigation at num_speculative_tokens=2). Co-authored-by: Markus Hartikainen <mahartik@amd.com> Signed-off-by: Frida Andersson <fanderss@amd.com>
The AITER gluon preshuffle kernel (_gluon_deepgemm_fp8_paged_mqa_logits_ preshuffle) performs unmasked buffer_store writes up to ~190 float32 elements past context_length in each logits row when block_size=64. With the previous exact-size allocation those stores corrupt the logits of the adjacent row, causing wrong top-k selection and degenerate output. Fix: introduce _get_paged_logits_buffer that allocates (rows, cols + _PAGED_LOGITS_COL_PADDING) where _PAGED_LOGITS_COL_PADDING=256. A non-contiguous [:rows, :cols] slice is intentionally avoided: deepgemm_fp8_paged_mqa_logits assumes contiguous output and would compute incorrect row offsets from a non-contiguous tensor. The full contiguous allocation ensures stride(0) = cols + 256 consistently; the padding columns absorb the OOB writes. top_k_per_row_decode takes logits.stride(0) and logits.stride(1) as explicit arguments and bounds iteration by seq_lens, so the extra columns are never read. A fresh allocation per call (no global cache) ensures each HIP graph bucket owns its own stable tensor pointer; a shared global reallocated for a larger bucket would leave earlier-captured graphs with dangling pointers on replay. Also fixes device="cuda" -> q_fp8.device so TP ranks > 0 allocate on the correct GPU. Validated: GSM8K 5-shot flexible-extract 0.9416 on TP4 with HIP graphs and block_size=64 (reference fork: 0.9409). Related: vllm-project#40643 (maeehart: same padding with caching, draft pending MAF investigation at num_speculative_tokens=2). Co-authored-by: Markus Hartikainen <mahartik@amd.com> Signed-off-by: Frida Andersson <fanderss@amd.com>
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Summary
Harden the ROCm sparse-MLA indexer for DeepSeek V3.2 decode on gfx950 (MI355X) against an intermittent HIP Memory Access Fault triggered by MTP speculative decoding. Three changes, shipped together:
deepgemm_fp8_paged_mqa_logitsaiter API (including the preshuffle path forblock_size == 64) instead of the older 3-stage_stage1+ Pythonsum(dim=0)pipeline. This is required anyway for MFMA-shaped decode on gfx950 withblock_size > 1; DSv3.2 already needs it and has been carrying the change as a private patch in its distribution image._get_paged_logits_buffer(...); DSv3.2 has 61 layers per decode step and the cache saves onetorch.full(-inf)per layer._PAGED_LOGITS_ROW_PADDING = 256float32 columns. Consumers see the logical shape; the downstreamtop_k_per_row_decodeop already takesstride(0)/stride(1)as explicit arguments, so the padding is stride-transparent.A companion aiter PR ROCm/aiter#2866 pairs with this one to add
mask=offset < max_model_lento unmaskedbuffer_storesites in the preshuffle kernel as kernel hygiene; the exact root-cause kernel for the MAF has not been pinned yet, so this PR stands on its own empirical evidence and does not depend on aiter#2866 for correctness.Motivation
On gfx950 (MI355X), enabling MTP speculative decoding for DeepSeek V3.2 against
vllm-project/vllmmain built with a stock aiter reliably reproduces an HIP Memory Access Fault during decode. A 20× MTPc=4sweep of the(random_input_len=1000, random_output_len=100)cell faulted on every run before these changes and completes 20 / 20 with zero MAFs after.What we know about the fault
main+ stock aiter + DSv3.2 + MTPnum_speculative_tokens >= 1on MI355X. Faults on every decode-heavy run without the padding; zero faults in 20 / 20 runs with it._cached_paged_logitslands and moves a subsequent overshoot (possibly from a downstream PyTorch-Inductor-generated fused kernel, e.g. atriton_poi_fused_*whose Triton backend lowers stores to uncheckedglobal_store_dword) away from the boundary of an adjacent allocation. Reproducing the fault withAMD_SERIALIZE_KERNEL=3 + AMD_LOG_LEVEL=4on the unpatched image to attribute it to a single kernel name is on the follow-up list.Relationship to aiter#2866
The companion aiter PR ROCm/aiter#2866 adds
mask=offset < max_model_lento the unmaskedbuffer_storesites in_gluon_deepgemm_fp8_paged_mqa_logits_preshuffle[_varctx]. It pairs well with this padding as belt-and-suspenders kernel hygiene, but since the exact root-cause kernel for the MAF has not been conclusively identified, this PR does not rely on aiter#2866 to remove the fault — the +256 padding is proven on its own.Why the new-API adoption
Upstream
maincurrently calls the older 3-stagedeepgemm_fp8_paged_mqa_logits_stage1API, which allocates(heads, B*next_n, max_model_len)and sums over heads in Python — fine for correctness but leaves the fused/preshuffle kernel (required for MFMA shapes on gfx950 withblock_size > 1) on the table. The DSv3.2 distribution image has been carrying a patchedrocm_aiter_mla_sparse.pythat already uses the fused API; this PR upstreams that adoption so the MI355X decode path works out-of-the-box against mainline vLLM.Changes
1.
_get_paged_logits_buffer(rows, cols, device)— a new module-private helper that returns a(rows, cols)float32 view initialised to-inf. Internally caches an over-allocated(rows, cols + _PAGED_LOGITS_ROW_PADDING)tensor across decode steps: repeated calls with matching(rows, cols, device)reuse the same storage._PAGED_LOGITS_ROW_PADDING = 256(one float32 row pitch widening).2.
rocm_fp8_paged_mqa_logits(..., block_size: int = 1)— adds ablock_sizekwarg. Whenblock_size > 1and the installed aiter build exposesdeepgemm_fp8_paged_mqa_logits, the fused path is used:Otherwise falls back to the existing
_stage1+out_qk.sum(dim=0)path unchanged.block_size=1(the default) preserves exactly today's behaviour on every existing codepath.3. Caller threads
block_size.rocm_aiter_sparse_attn_indexernow passesblock_size=kv_cache.shape[1]torocm_fp8_paged_mqa_logits. This is the same quantity already computed elsewhere in the file.Stride transparency (why the widened
stride(0)is safe)The only consumer of the logits returned by
rocm_fp8_paged_mqa_logitsin this file istorch.ops._C.top_k_per_row_decode, invoked immediately downstream:The C++ op (
large_context_topkincsrc/attention/topk.cu) pullsinput_stride = score.stride(0)into itsFastTopKParamsand only assertsscore.stride(1) == 1. Both are satisfied by our view (stride(0) = cols + 256,stride(1) = 1), so the widened-stride buffer is a fully legal input with no kernel change required.Cost
Per decode step (not per layer — the buffer is cached):
_PAGED_LOGITS_ROW_PADDING * batch * next_n * 4 B = 1 KiB × (batch × next_n). For a typical DSv3.2 MTP config withbatch = 128, next_n = 2, that's ~256 KiB extra VRAM total (once per process).colsper row. The extra 256 columns per row are never read or written.torch.fullon shape change, amortised to zero across 61 DSv3.2 decode layers by the cache.Validation
num_speculative_tokens=1,max_concurrency=4benchmark completed with zero MAFs against the same aiter build that was faulting on every run before the padding was added. Speculative decoding functional (positive MTP acceptance metrics). Serving stance:--async-scheduling, no--enforce-eager,gpu-memory-utilization 0.9,--tensor-parallel-size 4,--block-size 64,--max-num-batched-tokens 16384— i.e. the same production stance the DSv3.2 serving config ships with._stage1path unchanged —block_size=1(the default) skips the new branch entirely, so every existing caller is byte-identical at the bytecode level to today's behaviour.Back-compat
block_size: int = 1is a default-valued keyword arg — every existing caller is source- and ABI-compatible.block_size == 1(or the installed aiter build doesn't exportdeepgemm_fp8_paged_mqa_logits), the code takes the same_stage1branch as before, with zero line-level behavioural change._prefix) and carries explicit documentation of its lifetime and the fault it guards against.Test plan
c=4decode on MI355X with a stock aiter build — 20 / 20 no-MAF sweep.c=4decode on MI355X with an aiter build that has Add a model to the model executor list that is derived from RagTokenForGeneration model #2866 applied — confirm numerical parity with the current path._stage1fallback path (block_size = 1default) — unchanged behaviour.Cross-references
buffer_storemask on preshuffle)Essential Elements of an Effective PR Description Checklist