[ROCm][DeepSeek-V3.2][Perf] Enable gluon preshuffle indexer (block_size=64 + SHUFFLE layout)#41008
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…ze=64 + SHUFFLE layout) Based on vllm-project#32649 by @ganyi1996ppo — rebased onto current main with structural adaptations. Switch the ROCm sparse MLA backend from the stage1+reduce indexer path to the gluon preshuffle kernel (deepgemm_fp8_paged_mqa_logits with Preshuffle=True, KVBlockSize=64). This replaces a two-kernel pipeline (deepgemm_fp8_paged_mqa_logits_stage1 + reduce<float,sum>) with a single fused Triton kernel, yielding ~1 ms savings per decode iteration on MI355X TP4 at 1K context. Key changes: - ROCMAiterMLASparseBackend now inherits from AiterMLABackend to reuse FP8 KV cache infrastructure (dtype support, prefill path, metadata) - ROCMAiterMLASparseImpl inherits from AiterMLAImpl; forward_mqa overridden for sparse decode via mla_decode_fwd with topk indices - Added FP8 casting + q_scale/k_scale passing in _forward_sparse_mla - KV cache flattened for mla_decode_fwd when block_size > 1 - Triton indexer kernels use SHUFFLE layout (was NHD) - rocm_fp8_paged_mqa_logits uses gluon API when block_size > 1, falls back to stage1 otherwise - DeepseekV32IndexerBackend returns block_size=64 (was 1 on ROCm) - Parent-allocated oversized buffers released in metadata builder __init__ to save ~52 MB/layer Profiled result (1K input / 100 output, TP4 MI355X): Baseline: 21.9 ms/iter → Gluon: 18.2 ms/iter (includes run-to-run noise; conservative estimate ~1.5-2.0 ms real) Accuracy (GSM8K 5-shot): 0.9121 vs 0.9424 baseline — 3pp regression under investigation (likely FP8 scale handling or layout numerics). Signed-off-by: frida-andersson <fanderss@amd.com>
Allocate output tensor freshly each call instead of caching in _sparse_decode_out. The cached buffer was captured as read-only during HIP graph recording, causing "Write access to a read-only page" faults on replay. Also move current_platform import to module level. Made-with: Cursor
…cleanup Add defensive +256 column padding to _get_paged_logits_buffer to absorb OOB writes from the AITER preshuffle kernel (up to ~190 elements past context_length). Re-fill the cached buffer with -inf on every cache hit to prevent stale logits from prior steps corrupting top-k selection. This fixes a ~5pp GSM8K accuracy regression (0.89 → 0.94). Also: fix ruff I001 import ordering, move fp8_dtype inside FP8 branch. Co-authored-by: Markus Hartikainen <maeehart@users.noreply.github.com> Made-with: Cursor
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Code Review
This pull request updates the ROCM Aiter MLA sparse attention backend to support FP8 data types and larger block sizes (specifically block size 64). Key changes include the introduction of a paged logits buffer to prevent out-of-bounds writes, support for the 'SHUFFLE' layout in quantization and gather kernels, and integration with the new AITER paged MQA logits API. Feedback highlights critical issues regarding CUDA Graph compatibility due to dynamic sequence length usage, potential layout mismatches when block sizes are not 64, and a hardcoded device string that could cause failures in multi-GPU setups.
| decode_metadata.block_table, | ||
| decode_metadata.schedule_metadata, | ||
| max_model_len=max_model_len, | ||
| max_model_len=actual_max_seq_len, |
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Using actual_max_seq_len (which is the dynamic maximum sequence length of the current batch) as the max_model_len parameter is incompatible with CUDA Graphs. Since this value is a Python integer and changes every step, it will be baked into the graph during capture. Subsequent replays with a different actual maximum sequence length will use the stale value, leading to incorrect GEMM dimensions or memory corruption. You should use the constant max_model_len passed as an argument to the function to ensure graph stability.
| max_model_len=actual_max_seq_len, | |
| max_model_len=max_model_len, |
| num_tokens, | ||
| head_dim, | ||
| "NHD", | ||
| "SHUFFLE", |
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The quantization kernel is now hardcoded to use the "SHUFFLE" layout. However, the attention logic in rocm_fp8_paged_mqa_logits only enables Preshuffle=True when block_size == 64 (line 408) and falls back to the stage1 kernel for block_size == 1 (line 413). The stage1 kernel and the gluon kernel with Preshuffle=False expect the standard "NHD" layout. This inconsistency will lead to incorrect results for any block_size other than 64. The layout should be conditional on the block size.
| "SHUFFLE", | |
| "SHUFFLE" if block_size == 64 else "NHD", |
| k_cache_value.stride(0), | ||
| k_cache_scale.stride(0), | ||
| "NHD", | ||
| "SHUFFLE", |
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Similar to the indexer quantization kernel, this gather kernel should only use the "SHUFFLE" layout when the block size is 64 to maintain compatibility with the attention kernels and the fallback paths.
| "SHUFFLE", | |
| "SHUFFLE" if block_size == 64 else "NHD", |
| out_qk = torch.full( | ||
| (heads, batch_size * next_n, max_model_len), | ||
| float("-inf"), | ||
| device="cuda", |
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Hardcoding device="cuda" can cause runtime errors in multi-GPU environments or if the input tensors are on a specific device that is not the current default. It is safer to use the device of the input query tensor.
| device="cuda", | |
| device=q_fp8.device, |
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[ROCm][DeepSeek-V3.2][Perf] Enable gluon preshuffle indexer (block_size=64 + SHUFFLE layout)
Purpose
Switch the ROCm sparse MLA decode path from the two-kernel
deepgemm_fp8_paged_mqa_logits_stage1+reduce_sumflow to the fuseddeepgemm_fp8_paged_mqa_logits("gluon") API withPreshuffle=TrueandKVBlockSize=64. This eliminates the stage1+reduce pair and several auxiliary ops, cutting the sparse indexer kernel time by ~51%.Based on the gluon preshuffle work by @ganyi1996ppo in #32649 (rebased by @whx-sjtu). Incorporates the +256 logits padding fix from @maeehart (#40643). Supersedes #40643.
Changes
DeepseekV32IndexerBackendandROCMAiterMLASparseBackend.indexer_k_quant_and_cacheandcp_gather_indexer_k_quant_cachekernels, required by the gluon preshuffle kernel.deepgemm_fp8_paged_mqa_logitswithPreshuffle=True,KVBlockSize=64. Falls back tostage1+reduce_sumwhenblock_size == 1or on older AITER versions._get_paged_logits_buffer) with +256 column padding (credit @maeehart, #40643) to absorb preshuffle kernel OOB writes. Eliminates per-layertorch.fullallocation. Companion aiter fix: ROCm/aiter#2866.actual_max_seq_lenpassed to paged MQA logits instead ofmax_model_len, shrinking the GEMM problem size.fp8_e4m3,fp8_e5m2,fp8_e4m3fnuz,fp8_e5m2fnuz).outputtensor per call instead of cached buffer, preventing "Write access to a read-only page" faults.heads < 16.Files:
indexer.py(1 line),ops/rocm_aiter_mla_sparse.py,backends/mla/rocm_aiter_mla_sparse.py— 3 files, ~150 lines net.Test Result
Performance
Single profiled decode step, 1K input / 100 output, TP4, 4× MI355X.
Before (stage1 + reduce_kernel, 14.2 µs + reduce):
After (gluon preshuffle, 4.9 µs):
Accuracy (GSM8K 5-shot, exact_match, TP4)
Test Plan
Dependencies
deepgemm_fp8_paged_mqa_logitswithPreshufflekwarg (added in ROCm/aiter#1754). Falls back tostage1+reduce_sumon older versions.Related PRs
mask=offset < max_model_lento preshuffle kernelbuffer_storesites.