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[ROCm][Bugfix] Add +256 col guard to preshuffle logits buffer (DSv3.2)#41810

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frida-andersson:rocm/dsv32-preshuffle-logits-padding
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[ROCm][Bugfix] Add +256 col guard to preshuffle logits buffer (DSv3.2)#41810
frida-andersson wants to merge 1 commit intovllm-project:mainfrom
frida-andersson:rocm/dsv32-preshuffle-logits-padding

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@frida-andersson frida-andersson commented May 6, 2026

Summary

The AITER gluon preshuffle kernel (_gluon_deepgemm_fp8_paged_mqa_logits_preshuffle) performs unmasked buffer_store writes up to ~190 float32 elements past context_length in each logits row when block_size=64. With the previous exact-size allocation those stores corrupt the logits of the adjacent row, causing wrong top-k selection and degenerate output.

Solution

Introduce _get_paged_logits_buffer which allocates (rows, cols + _PAGED_LOGITS_COL_PADDING) where _PAGED_LOGITS_COL_PADDING=256. The returned tensor is contiguous with stride(0)=cols+256, stride(1)=1. The only consumer, top_k_per_row_decode, already takes logits.stride(0) and logits.stride(1) as explicit arguments and bounds iteration by seq_lens, so the wider row stride is fully transparent.

A fresh allocation is used on every call (rather than caching) so that each HIP graph bucket retains its own stable tensor pointer; caching a shared global that gets reallocated for a larger batch bucket would leave earlier-captured graphs with dangling pointers on replay.

Also fixes device="cuda"q_fp8.device so TP ranks > 0 allocate on the correct GPU.

Test plan

  • GSM8K 5-shot flexible-extract: 0.9416 on TP4 with HIP graphs and --block-size 64 (reference fork: 0.9409)
  • Existing behaviour with block_size=1 is unchanged (takes the _stage1 path, _get_paged_logits_buffer is never called)

Dependency: #41760 (correctness fix for DSv3.2 TP4 HIP graphs).

Related

Co-authored-by: Markus Hartikainen maeehart@users.noreply.github.com

@frida-andersson frida-andersson requested a review from tjtanaa as a code owner May 6, 2026 11:12
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@mergify mergify Bot added rocm Related to AMD ROCm v1 bug Something isn't working labels May 6, 2026
@github-project-automation github-project-automation Bot moved this to Todo in AMD May 6, 2026
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mergify Bot commented May 6, 2026

This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @frida-andersson.

https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/working-with-forks/syncing-a-fork

@mergify mergify Bot added the needs-rebase label May 6, 2026
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Code Review

This pull request introduces a helper function, _get_paged_logits_buffer, which allocates logits buffers with additional column padding to safely absorb out-of-bounds stores from the AITER preshuffle kernel. It also ensures that fresh tensors are allocated to maintain stability during HIP graph captures. Review feedback points out that the function currently returns the over-allocated tensor's logical shape, which could break downstream code or cause inconsistencies with fallback paths. It is recommended to return a sliced view of the tensor so that the logical dimensions remain correct while the underlying storage retains the necessary padding.

Comment on lines +24 to +47
def _get_paged_logits_buffer(
rows: int, cols: int, device: torch.device
) -> torch.Tensor:
"""Return a fresh (rows, cols + _PAGED_LOGITS_COL_PADDING) float32 tensor
pre-filled with -inf.

Allocating fresh each call is intentional: vLLM captures a separate HIP
graph for every batch-size bucket. Each graph records the pointer of the
tensor that was live at capture time. If we handed out a cached tensor and
then reallocated it for a larger bucket, the old graph would replay against
a freed pointer. The fresh allocation ensures every captured graph owns
its own stable buffer for the lifetime of the graph.

The extra _PAGED_LOGITS_COL_PADDING columns guard against OOB stores from
the AITER preshuffle kernel, which does unmasked buffer_store up to ~190
elements past context_length. top_k_per_row_decode uses explicit strides
and seq_lens so the extra columns never affect the selected top-k indices.
"""
return torch.full(
(rows, cols + _PAGED_LOGITS_COL_PADDING),
float("-inf"),
device=device,
dtype=torch.float32,
)
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high

The _get_paged_logits_buffer function currently returns a tensor with a logical width of cols + _PAGED_LOGITS_COL_PADDING. This causes rocm_fp8_paged_mqa_logits to return a tensor of shape (rows, max_model_len + 256), which is inconsistent with its fallback path (fp8_paged_mqa_logits_torch) and its docstring (which specifies a shape of [B * next_n, max_model_len]). This inconsistency can lead to errors in downstream code that expects the exact max_model_len width, such as when performing reshapes, views, or assignments to pre-allocated buffers.

To fix this while preserving the padding in the underlying storage for the AITER kernel, you should return a slice of the over-allocated tensor. This maintains the correct logical shape for the caller while keeping the wider stride that protects against out-of-bounds writes. Since top_k_per_row_decode already uses explicit strides, it will continue to function correctly with the sliced view.

def _get_paged_logits_buffer(
    rows: int, cols: int, device: torch.device
) -> torch.Tensor:
    """Return a fresh (rows, cols) float32 tensor pre-filled with -inf.

    Allocating fresh each call is intentional: vLLM captures a separate HIP
    graph for every batch-size bucket.  Each graph records the pointer of the
    tensor that was live at capture time.  If we handed out a cached tensor and
    then reallocated it for a larger bucket, the old graph would replay against
    a freed pointer.  The fresh allocation ensures every captured graph owns
    its own stable buffer for the lifetime of the graph.

    The extra _PAGED_LOGITS_COL_PADDING columns in the underlying storage
    guard against OOB stores from the AITER preshuffle kernel, which does
    unmasked buffer_store up to ~190 elements past context_length.
    top_k_per_row_decode uses explicit strides and seq_lens so the extra
    columns never affect the selected top-k indices.
    """
    return torch.full(
        (rows, cols + _PAGED_LOGITS_COL_PADDING),
        float("-inf"),
        device=device,
        dtype=torch.float32,
    )[:, :cols]

The AITER gluon preshuffle kernel (_gluon_deepgemm_fp8_paged_mqa_logits_
preshuffle) performs unmasked buffer_store writes up to ~190 float32
elements past context_length in each logits row when block_size=64.
With the previous exact-size allocation those stores corrupt the logits
of the adjacent row, causing wrong top-k selection and degenerate output.

Fix: introduce _get_paged_logits_buffer that allocates (rows,
cols + _PAGED_LOGITS_COL_PADDING) where _PAGED_LOGITS_COL_PADDING=256.
A non-contiguous [:rows, :cols] slice is intentionally avoided:
deepgemm_fp8_paged_mqa_logits assumes contiguous output and would compute
incorrect row offsets from a non-contiguous tensor. The full contiguous
allocation ensures stride(0) = cols + 256 consistently; the padding
columns absorb the OOB writes. top_k_per_row_decode takes logits.stride(0)
and logits.stride(1) as explicit arguments and bounds iteration by
seq_lens, so the extra columns are never read.

A fresh allocation per call (no global cache) ensures each HIP graph
bucket owns its own stable tensor pointer; a shared global reallocated
for a larger bucket would leave earlier-captured graphs with dangling
pointers on replay.

Also fixes device="cuda" -> q_fp8.device so TP ranks > 0 allocate on
the correct GPU.

Validated: GSM8K 5-shot flexible-extract 0.9416 on TP4 with HIP graphs
and block_size=64 (reference fork: 0.9409).

Related: vllm-project#40643 (maeehart: same padding with caching, draft pending MAF
investigation at num_speculative_tokens=2).

Co-authored-by: Markus Hartikainen <mahartik@amd.com>
Signed-off-by: Frida Andersson <fanderss@amd.com>
@frida-andersson frida-andersson force-pushed the rocm/dsv32-preshuffle-logits-padding branch from 51552ea to 93e5a57 Compare May 6, 2026 18:41
@github-project-automation github-project-automation Bot moved this from Todo to Done in AMD May 6, 2026
@mergify mergify Bot added ci/build frontend llama Related to Llama models multi-modality Related to multi-modality (#4194) mistral Related to Mistral models performance Performance-related issues qwen Related to Qwen models gpt-oss Related to GPT-OSS models nvidia intel-gpu Related to Intel GPU cpu Related to CPU backends structured-output speculative-decoding tpu Related to Google TPUs tool-calling labels May 6, 2026
@mergify mergify Bot added the kv-connector label May 6, 2026
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Superseded by #41856 (branch history was corrupted by a shallow-clone amend; this PR cannot be reopened)

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bug Something isn't working ci/build cpu Related to CPU backends deepseek Related to DeepSeek models frontend gpt-oss Related to GPT-OSS models intel-gpu Related to Intel GPU kv-connector llama Related to Llama models mistral Related to Mistral models multi-modality Related to multi-modality (#4194) nvidia performance Performance-related issues qwen Related to Qwen models rocm Related to AMD ROCm speculative-decoding structured-output tool-calling tpu Related to Google TPUs v1

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