[Build] Add support for Ascend950 chip#7151
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…dC::PipeBarrier<PIPE_ENUM>() Signed-off-by: linfeng-yuan <1102311262@qq.com>
Signed-off-by: linfeng-yuan <1102311262@qq.com>
Signed-off-by: linfeng-yuan <1102311262@qq.com>
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Summary of ChangesHello, I'm Gemini Code Assist1! I'm currently reviewing this pull request and will post my feedback shortly. In the meantime, here's a summary to help you and other reviewers quickly get up to speed! This pull request primarily extends hardware support to include the Ascend950 chip. This involves modifications to the build configuration to correctly identify the new chip and manage operator compatibility. Additionally, a widespread refactoring was performed to update the Highlights
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Code Review
This pull request introduces support for the Ascend950 chip and performs a large-scale refactoring of pipe_barrier calls.
The key changes are:
- Ascend950 Support: Build scripts (
CMakeLists.txt,setup.py) are updated to recognize the Ascend950 chip, setting the device type to 'A5' and adding a_ASCEND950compile definition. - Operator Disabling: A number of operators are disabled for the Ascend950 target by using the
_ASCEND950preprocessor directive incsrc/torch_binding.cpp. This is consistent with the build script changes that exclude the corresponding kernels from compilation. - Refactoring: All occurrences of
pipe_barrier()have been refactored toAscendC::PipeBarrier<>()across numerous kernel files. This appears to be a modernization effort to use a namespaced and templated version of the API, which improves code clarity and consistency.
The changes are logical and well-executed. The new chip support is implemented cleanly, and the refactoring is applied consistently.
As per the repository's style guide, I'm suggesting an updated Pull Request title and summary:
Suggested PR Title:
[Build][Feature] Add support for Ascend950 chipSuggested PR Summary:
### What this PR does / why we need it?
This PR adds support for the Ascend950 chip. This includes:
- Updating build scripts (`CMakeLists.txt` and `setup.py`) to recognize the Ascend950 chip and set appropriate compilation flags.
- Disabling a set of custom operators that are not yet supported on the Ascend950 hardware target.
- Performing a codebase-wide refactoring of `pipe_barrier()` calls to the namespaced `AscendC::PipeBarrier<>()` for improved code consistency and adherence to the latest API standards.
### Does this PR introduce _any_ user-facing change?
Yes, this PR adds support for a new hardware target, the Ascend950.
### How was this patch tested?
CI should be run to ensure all existing tests pass on supported platforms. Specific tests should be added and executed on an Ascend950 device to validate the new support and ensure that the enabled operators function correctly.Signed-off-by: linfeng-yuan <1102311262@qq.com>
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| # There are some customed operators which aren't implemented | ||
| # with batch invariant in vllm-ascend, we need to disable them. | ||
| if vllm_is_batch_invariant(): | ||
| if vllm_is_batch_invariant() or get_ascend_device_type() == AscendDeviceType.A5: |
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Currently, execution of some ops do not check enable_custom_op() and support fallback calling with torch_npu (e.g., init_routing_custom, gating_top_k_custom, etc.). Currently, we can use the pta API with CANN 8.5.1. We plan to investigate the affects and delete these unnecessary custom ops ASAP.
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OP_LIST: [enabled, disabled] add comments here
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We've added comments to refer reader to #7157 now.
…op support link Signed-off-by: linfeng-yuan <1102311262@qq.com>
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…to qwen3next_graph * 'main' of https://github.com/vllm-project/vllm-ascend: (88 commits) [main][bugfix] Fixed the problem of speculative decoding in FULL mode (vllm-project#7148) fixed fia pad logic in graph mode. (vllm-project#7144) [Doc] fix DSV3.1 PD configs (vllm-project#7187) refactor: add a check before layer_sharding logging (vllm-project#7186) [Build] Add support for Ascend950 chip (vllm-project#7151) Revert "[CI] fix skiped e2e test when upgrade vllm version (vllm-project#6654)" (vllm-project#7166) [MODELRUNNERV2]fix penality ops (vllm-project#7013) [Bugfix][LoRA] Fix the issue when enable LoRA + tp + fully_sharded_loras (vllm-project#6650) [KV Pool]get_num_new_matched_tokens return 0 if token length < block_size (vllm-project#7146) [CI] Build Image for v0.16.0rc1 (vllm-project#7155) [CI] Skip `test_mooncake_layerwise_connector.py` in `ut` (vllm-project#7147) [BugFix]Fix recomputed scheduler bug (vllm-project#7137) [Model] Support Minimax-m2.5 on NPU (vllm-project#7105) [P/D]Mooncake Layerwise Connector supports hybrid attention manager with multiple kvcache groups (vllm-project#7022) Add patch_qwen3_5 for triton ops fused_recurrent_gated_delta_rule (vllm-project#7109) [Doc][ReleaseNote] Add release notes for v0.16.0rc1 (vllm-project#7067) [Misc] Download on both hk and guiyang region (vllm-project#7129) [bugdix] The problem that the w4a8 weight fails to be loaded when the EP is not enabled is resolved. (vllm-project#7090) [eagle][cp] fix eagle_cp enable bug2 (vllm-project#7079) [CI]Upgrade niglty multi-node-tests max-parallel to 2 (vllm-project#7035) ...
### What this PR does / why we need it? This PR adds support for the Ascend950 chip. This includes: - Updating build scripts (`CMakeLists.txt` and `setup.py`) to recognize the Ascend950 chip and set appropriate compilation flags. - Disabling a set of custom operators that are not yet supported on the Ascend950 hardware target. - Performing a codebase-wide refactoring of `pipe_barrier()` calls to the namespaced `AscendC::PipeBarrier<>()` for improved code consistency and adherence to the latest API standards. Ascend950DT e2e passed (Qwen3-32B-MXFP8) and CI passed - vLLM version: v0.16.0 - vLLM main: vllm-project/vllm@4034c3d --------- Signed-off-by: linfeng-yuan <1102311262@qq.com>
What this PR does / why we need it?
This PR adds support for the Ascend950 chip. This includes:
CMakeLists.txtandsetup.py) to recognize the Ascend950 chip and set appropriate compilation flags.pipe_barrier()calls to the namespacedAscendC::PipeBarrier<>()for improved code consistency and adherence to the latest API standards.Does this PR introduce any user-facing change?
Yes, this PR adds support for a new hardware target, the Ascend950.
How was this patch tested?
Ascend950DT e2e passed (Qwen3-32B-MXFP8) and CI passed