Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

The next generation of OpenLane, rewritten from scratch with a modular architecture

Cryptocurrency ASIC mining hardware monitor using a simple web interface

Allo: A Programming Model for Composable Accelerator Design

A seamless python to Cadence Virtuoso Skill interface

HW Design: A Functional Approach

Control and status register code generator toolchain

A simplified and standardized interface for Bitcoin ASICs.

Control and Status Register map generator for HDL projects

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

An open-source HDL register code generator fast enough to run in real time.

TinyTapeout submission with the SN76489 Digital Complex Sound Generator (DCSG) programmable sound generator (PSG) chip from Texas Instruments.

Generate UVM register model from compiled SystemRDL input

Primitives for GF180MCU provided by GlobalFoundries.

tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles

Antminer monitor and auto-restart tool (Watchdog). 100% Free Software (Libre)

Import and export IP-XACT XML register models

A Heterogeneous Platform Deep Learning Compiler Framework from EdgeCortix

Unofficial python api for MicroBT Whatsminer ASICs