Digital logic design tool and simulator
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Updated
Dec 23, 2024 - Java
Digital logic design tool and simulator
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
Verilator open-source SystemVerilog simulator and lint system
GPGPU microprocessor architecture
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Must-have verilog systemverilog modules
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
HDL libraries and projects
Haskell to VHDL/Verilog/SystemVerilog compiler
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
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