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feat(hicache): add KVCR L3 storage with router-guided peer restore - #43635
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ziqifan617 wants to merge 9 commits into
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ziqifan617 wants to merge 9 commits into
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Signed-off-by: Ziqi Fan <ziqif@nvidia.com>
This was referenced Oct 11, 2026
The PD decode HiCache path queried and prefetched L3 without the request's kv_hints, so a decode worker could never reach a hinted peer. Thread them through query_storage_hit_length and the decode prefetch, like the scheduler's prefetch path already does. Signed-off-by: linhu-nv <linhu@nvidia.com> (cherry picked from commit 228cd4b) Signed-off-by: Ziqi Fan <ziqif@nvidia.com>
DeepSeek V4's KV pool is a LogicalHostPool without payload, so KVCR registers no layout for it. A batch_exists_v2 call without pool transfers then queried nothing and reported every page present. That is the path of batch_exists, which PD decode uses to size its L3 hit. A decode worker then allocated and prefetched pages that no pool held. Answer a bare query from the registered pools that hold every stored page (the non-trailing pools). Calls with explicit pool transfers are unchanged. Signed-off-by: linhu-nv <linhu@nvidia.com> (cherry picked from commit 1538ea5) Signed-off-by: Ziqi Fan <ziqif@nvidia.com>
Cover request hints through the PD-decode probe/prefetch path and logical-anchor queries across physical pools. Preserve Lin Hu source fixes, and reject bare queries with no all-pages evidence. Signed-off-by: Ziqi Fan <ziqif@nvidia.com>
Signed-off-by: Ziqi Fan <ziqif@nvidia.com>
…fig" This reverts commit adfe7b1. Signed-off-by: Ziqi Fan <ziqif@nvidia.com>
Signed-off-by: Ziqi Fan <ziqif@nvidia.com>
Use private anonymous DRAM pools, bounded delivery pipelining, and configurable prefetch query batching. Add optional scheduler thread-switch control and ownership-scoped NUMA allocation with strict registration evidence checks. Keep defaults and workload semantics intact; include CPU contract tests and CLI documentation. Preserve the existing GC-observer removal. No Mooncake implementation or benchmark reports included.
This was referenced Oct 21, 2026
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Superseded by the smaller review slices #45646 → #45647 → #45649. These preserve the HiCache implementation and separate initial enablement from optional performance tuning. Closing this monolithic PR to consolidate review; its branch and benchmark history remain available for reference. The replacement PRs remain drafts with their documented validation and merge gates. |
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Motivation
Add KVCR as an optional HiCacheStorage L3 backend for local and cross-replica KV reuse over NIXL/UCX.
Together with Dynamo #16117, this enables router-guided peer restore through in-process
python -m dynamo.sglang: Dynamo publishes candidate sources and forwards request hints; this PR implements storage access and restores the data through HiCache.This is the HiCacheStorage route, not linker/direct-HBM mode. Remote delivery does not require an intermediate destination-side KVCR cache allocation, and unpinned SGLang host pages are never offered as peer sources. Local L3 works without Dynamo; router-directed cross-replica discovery needs the companion or another compatible hint producer.
Modifications
kvcrbackend with page-first host layouts; register physical components once and use indexedRegionDescriptor/MemoryRefAPIs for multi-component, multi-pool IO.kv_hintsthrough scheduler prefetch, PD-decode probes/prefetch, deferred tickets, and trailing-pool reads. Reject bare logical-anchor queries without physical ALL_PAGES evidence.Accuracy Tests
git diff --checkpassed. The October 15 follow-ups have CPU coverage; a new GPU/model run and full upstream CI are not claimed.Speed Tests and Profiling
Combined IO, read batching, sharing, and recency alignment are opt-in. No inference-speed result is claimed for the latest head; expensive diagnostics remain disabled by default.
Dependencies and Scope
startup_timeout_secondsadditionally requires KVCR #82; transfer deadlines are separate.Review
storage/kvcr/{layout,hints,kvcr_store}.py, then controller batching/boundary changes and regressions.Checklist
CI States
Latest PR Test (Base): ❌ Missing
run-cilabel -- add it to run CI tests.Latest PR Test (Extra): ❌ Blocked --
run-ciis required first.Latest PR Test (AMD ROCm 10): ➖ No AMD PR run found for this commit.