[CPULLVM] - Prepare for LIBCXX tests enablement RISCV. by pawan-nirpal-031 · Pull Request #469 · qualcomm/cpullvm-toolchain

Pawan Nirpal (pawan-nirpal-031) · 2026-07-03T08:13:29Z

Manage fixes for RISC-V LIBCXX tests enablement.

We add xfails for the following variants, but do not enable all of them due to CI timeout limit.

riscv32gc_ilp32d
riscv32imac_ilp32
riscv32imac_ilp32_nopic
riscv32imac_zba_zbb_ilp32
riscv32imac_zba_zbb_ilp32_nopic
riscv32imac_zcb_zcmp_ilp32_nopic
riscv32imac_zcb_zcmp_zba_zbb_ilp32_nopic
riscv32imafc_ilp32f
riscv32imafc_zba_zbb_ilp32f
riscv32imafc_zcb_zcmp_zba_zbb_ilp32f
riscv64gc_lp64_nopic
riscv64gc_lp64d_nopic
riscv64gc_zba_zbb_lp64_nopic
riscv64gc_zba_zbb_lp64d_nopic
riscv64imac_lp64_nopic

We only enable the following riscv variants.

riscv32gc_ilp32d
riscv32imac_ilp32
riscv32imac_zba_zbb_ilp32_nopic
riscv32imafc_zcb_zcmp_zba_zbb_ilp32f
riscv64gc_lp64_nopic
riscv64gc_zba_zbb_lp64d_nopic
riscv64imac_lp64_nopic

Signed-off-by: Pawan Nirpal <pnirpal@qti.qualcomm.com>

Pawan Nirpal (pawan-nirpal-031) · 2026-07-03T08:23:17Z

Jonathon Penix (@jonathonpenix) Ana Pazos (@apazos) Shreeyash Pandey (@bojle) Garvit Gupta (@quic-garvgupt) please review.

Pawan Nirpal (pawan-nirpal-031) · 2026-07-03T09:49:53Z

https://github.com/qualcomm/cpullvm-toolchain/actions/runs/28660075798

Pass for.
riscv32gc_ilp32d
riscv32imac_ilp32
riscv32imac_ilp32_nopic
riscv32imac_zba_zbb_ilp32
riscv32imac_zba_zbb_ilp32_nopic
ninja check-cxx-riscv32imac_zcb_zcmp_ilp32_nopic

Shreeyash Pandey (bojle) · 2026-07-03T10:07:14Z

        ),
        XFail(
-            name="long-double-picolibc-aarch64",
+            name="ong-double-picolibc-aarch64-riscv",


Is this a typo? (long -> ong)

Oops yes. Thanks for the observation.

Pankaj Gode (pgodeq) · 2026-07-03T17:38:29Z

Would you be enabling LIBCXX tests for riscv variant: riscv32im_zba_zbb_zbc_zbs_zca_zcb_zcmp_ilp32_nothreads_nopic ?

If this is planned, then I would abandon my PR #465.

Pawan Nirpal (pawan-nirpal-031) · 2026-07-03T19:18:06Z

Would you be enabling LIBCXX tests for riscv variant: riscv32im_zba_zbb_zbc_zbs_zca_zcb_zcmp_ilp32_nothreads_nopic ?

If this is planned, then I would abandon my PR #465.

Yes Pankaj, I have those variants planned for a following PR. Due to CI timeout we are brining in riscv variants in batches.

Pawan Nirpal (pawan-nirpal-031) · 2026-07-03T19:20:23Z

CI build pass for https://github.com/qualcomm/cpullvm-toolchain/actions/runs/28667521664/job/85022776504?pr=469 the following.

ninja check-cxx-riscv32gc_ilp32d
ninja check-cxx-riscv32imac_ilp32
ninja check-cxx-riscv32imac_ilp32_nopic
ninja check-cxx-riscv32imac_zba_zbb_ilp32
ninja check-cxx-riscv32imac_zba_zbb_ilp32_nopic
ninja check-cxx-riscv32imac_zcb_zcmp_ilp32_nopic
ninja check-cxx-riscv32imac_zcb_zcmp_zba_zbb_ilp32_nopic
ninja check-cxx-riscv32imafc_ilp32f
ninja check-cxx-riscv32imafc_zba_zbb_ilp32f
ninja check-cxx-riscv32imafc_zcb_zcmp_zba_zbb_ilp32f

Jonathon Penix (jonathonpenix) · 2026-07-06T18:00:31Z

Either:

Include runs that (in aggregate) cover all the variants you are handling in this PR -OR-
Please remove the changes for variants unrelated to what you're saying you're enabling/testing in this PR

And, repeating this from elsewhere:

For test_libcxx.sh, let's just start with a subset of the RISC-V variants:
riscv32imac_ilp32
riscv32imac_zba_zbb_ilp32_nopic
riscv32imafc_zcb_zcmp_zba_zbb_ilp32f
riscv32gc_ilp32d
riscv32im_xqci_ilp32_nothreads_nopic
riscv64imac_lp64_nopic
riscv64gc_lp64_nopic
riscv64gc_zba_zbb_lp64d_nopic

Either just leave test_libcxx.sh unchanged and fix it up at the end, or just add the subset of variants tested in this PR and mentioned above.

Jonathon Penix (jonathonpenix) · 2026-07-06T18:04:51Z

And, repeating from elsewhere again--please only include variants that have ENABLE_LIBC_TESTS/ENABLE_CXX_LIBS/ENABLE_LIBCXX_TESTS set to ON

Pawan Nirpal (pawan-nirpal-031) · 2026-07-07T15:59:25Z

And, repeating from elsewhere again--please only include variants that have ENABLE_LIBC_TESTS/ENABLE_CXX_LIBS/ENABLE_LIBCXX_TESTS set to ON

Either:

Include runs that (in aggregate) cover all the variants you are handling in this PR -OR-

Please remove the changes for variants unrelated to what you're saying you're enabling/testing in this PR

And, repeating this from elsewhere:

For test_libcxx.sh, let's just start with a subset of the RISC-V variants:
riscv32imac_ilp32
riscv32imac_zba_zbb_ilp32_nopic
riscv32imafc_zcb_zcmp_zba_zbb_ilp32f
riscv32gc_ilp32d
riscv32im_xqci_ilp32_nothreads_nopic
riscv64imac_lp64_nopic
riscv64gc_lp64_nopic
riscv64gc_zba_zbb_lp64d_nopic

Either just leave test_libcxx.sh unchanged and fix it up at the end, or just add the subset of variants tested in this PR and mentioned above.

Testing all variants added in the xfails.

Ana Pazos (apazos) · 2026-07-07T23:34:23Z

@@ -240,7 +241,7 @@ def check_r52_warning():
                         "on ARMv7-A/ARMv8 with NEON. Compiler bug; exclude until fixed.",
        ),
        XFail(
-            name="long-double-picolibc-aarch64",
+            name="long-double-picolibc-aarch64-riscv",


I think we should not merge xfails for different targets, just create separate xfail configs.

If the failure/testnames/descriptions are otherwise identical, I guess I have a weak preference for merging them just to not maintain this stuff twice.

But if they diverge on any of the failure cause/testnames/descriptions, I'm definitely in favor of splitting.

Ana Pazos (@apazos) I also have a slight preference for keeping them together to avoid duplication of cause/testnames/descriptions. If they diverge as mentioned by Jonathon Penix (@jonathonpenix) it should surely be split.

Ana Pazos (apazos) · 2026-07-07T23:42:08Z

+                        "infrastructure limitations, not test bugs.",
+        ),
+        XFail(
+            name="ios-xalloc-atomic-nothreads-riscv",


isn't there an easier way to xfail all the tests at once without listing each?

Excluded tests should be able to use regexes in the testnames rather than just raw names.

I don't know if there is a relatively terse regex you can write that actually captures the correct set of things though.

I guess overall this doesn't seem like the right way to be handling this--if there is this much that is broken, I think we should be:

Checking if there is something we should be configuring in our libc++ builds for these variants to disable this sort of stuff that we currently aren't (see ex: here where we configure certain features--is there something we can disable to tell libc++ not to assume we have atomic support?).

Checking if there is something we should be adding to libc++ to handle this sort of thing

Not testing these variants in the meantime.

I don't think XFAIL-ing however many hundreds of tests is something we want to be doing short or long term.

I was skeptical too about doing this, I did explore if there's anything due to config that may be causing this failure. I/Claude was not able to come up with anything that was standard and acceptable solution for this. The Same issue is seen in libcxxabi enablement https://github.com/qualcomm/cpullvm-toolchain/pull/341/changes#diff-146802d63a83077720f5c2eb7d5ec6460d2304104383ee1acd4810438d0be5b2R155

I will try some more to find any option like fix. If not at all possible for the time being, I'm in favour of not testing the variants these tests fail for.

Edit, we have a pretty simple fix for it. Added that, CI is clean now.

Pawan Nirpal (pawan-nirpal-031) · 2026-07-08T11:21:10Z

CI All pass https://github.com/qualcomm/cpullvm-toolchain/actions/runs/28925976231/job/85813553924?pr=469 for the following variants.

ninja check-cxx-riscv32imc_ilp32_nothreads_nopic
ninja check-cxx-riscv32imc_zba_zbb_zbc_zbs_ilp32_nothreads_nopic
ninja check-cxx-riscv32im_zba_zbb_zbc_zbs_zca_zcb_zcmp_ilp32_nothreads_nopic
ninja check-cxx-riscv32im_xqci_ilp32_nothreads_nopic
ninja check-cxx-riscv64gc_lp64_nopic
ninja check-cxx-riscv64gc_lp64d_nopic
ninja check-cxx-riscv64gc_zba_zbb_lp64_nopic
ninja check-cxx-riscv64gc_zba_zbb_lp64d_nopic
ninja check-cxx-riscv64imac_lp64_nopic
ninja check-cxx-riscv64imc_lp64_nothreads_nopic

Pawan Nirpal (pawan-nirpal-031) · 2026-07-10T13:54:42Z

CI success for https://github.com/qualcomm/cpullvm-toolchain/actions/runs/29234971715/job/86767437393?pr=469

ninja check-cxx-riscv64gc_lp64_nopic
ninja check-cxx-riscv64gc_lp64d_nopic
ninja check-cxx-riscv64gc_zba_zbb_lp64_nopic
ninja check-cxx-riscv64gc_zba_zbb_lp64d_nopic
ninja check-cxx-riscv64imac_lp64_nopic

libc++ test failures with configs without atomics are disabled issue filed Make ios_base::xalloc non-atomic with LIBCXX_ENABLE_THREADS=OFF. by efriedma-quic · Pull Request #20… ;

Jonathon Penix (jonathonpenix)

Please update the description to reflect what the PR is doing/enabling.

Jonathon Penix (jonathonpenix) · 2026-07-10T20:42:23Z

Again #469 (comment)

Variants without 'a' can be omitted from the list in the link for now (so, the xqci one).

The following from the list is already removed, please check again.

riscv32im_xqci_ilp32_nothreads_nopic.

All those variants without atomic libs support, have been removed, I believe there's none here from that list that doesn't have the atomics support.

I say "Variants without..." only to say that the list linked above does not need to be implemented verbatim given the decisions that have since been made around variants without 'a'.

If that is done, then great! Nothing needs to change on that front.

I say "Again #469 (comment)" as again I think we need to start with a subset of these variants in test_libcxx.sh to have a chance of running these tests once this is merged.

If you disagree, that's fine--but please say so/say why.

I say "Variants without..." only to say that the list linked above does not need to be implemented verbatim given the decisions that have since been made around variants without 'a'.
If that is done, then great! Nothing needs to change on that front.

It is. Thanks.

I say "Again #469 (comment)" as again I think we need to start with a subset of these variants in test_libcxx.sh to have a chance of running these tests once this is merged.
If you disagree, that's fine--but please say so/say why.

Done too. We schedule only the following riscv variants.

riscv32gc_ilp32d
riscv32imac_ilp32
riscv32imac_zba_zbb_ilp32_nopic
riscv32imafc_zcb_zcmp_zba_zbb_ilp32f
riscv64gc_lp64_nopic
riscv64gc_zba_zbb_lp64d_nopic
riscv64imac_lp64_nopic

Signed-off-by: Pawan Nirpal <pnirpal@qti.qualcomm.com>

…blement

Signed-off-by: Pawan Nirpal <pnirpal@qti.qualcomm.com>

Jonathon Penix (jonathonpenix) · 2026-07-13T22:36:51Z

Please update the description to reflect what the PR is doing/enabling.

Ping

Signed-off-by: Pawan Nirpal <pnirpal@qti.qualcomm.com>

Pawan Nirpal (pawan-nirpal-031) · 2026-07-14T06:01:15Z

Please update the description to reflect what the PR is doing/enabling.

Ping

Updated, please suggest if this works or needs any change. This was deferred as the preference to run which variants was still to be decided.

Jonathon Penix (jonathonpenix)

Thanks Pawan Nirpal (@pawan-nirpal-031)

Jonathon Penix (jonathonpenix) · 2026-08-14T23:21:51Z

/cherry-pick 5193d63

cpullvmbot (cpullvmbot) · 2026-08-14T23:28:56Z

/pull-request #598

@jonathonpenix

…enablement RISCV. (#469) (#598) Backport 5193d63 Requested by: @jonathonpenix Signed-off-by: Pawan Nirpal <pnirpal@qti.qualcomm.com> Co-authored-by: Pawan Nirpal <pnirpal@qti.qualcomm.com>

Previously, xqci variants were omitted as we saw huge numbers of libc++ test failures in variants without 'a' (see #469) and at the time we didn't have any xqci variants with 'a'. We do now (and these variants turn on C++ libs and `ENABLE_LIBCXX_TESTS`) so add one such variant in the scheduled libc++ tests--it should be clean. Signed-off-by: Jonathon Penix <jpenix@qti.qualcomm.com>

Pawan Nirpal (pawan-nirpal-031) added 8 commits May 21, 2026 06:01

[CPULLVM] - Enable testing infra changes for rtlibs testing

5e79fdf

Signed-off-by: Pawan Nirpal <pnirpal@qti.qualcomm.com>

address comments and some more infra fixes

64ab51e

Signed-off-by: Pawan Nirpal <pnirpal@qti.qualcomm.com>

revert changes that are not required anymore handled elsewhere

731aeb7

Signed-off-by: Pawan Nirpal <pnirpal@qti.qualcomm.com>

no reorder in start group

8af9cca

Signed-off-by: Pawan Nirpal <pnirpal@qti.qualcomm.com>

Merge branch 'qualcomm:qualcomm-software' into qualcomm-software

b38c753

Merge branch 'qualcomm:qualcomm-software' into qualcomm-software

0f03d94

Merge branch 'qualcomm:qualcomm-software' into qualcomm-software

b634753

Merge branch 'qualcomm:qualcomm-software' into qualcomm-software

4443529

Pawan Nirpal (pawan-nirpal-031) requested a review from Jonathon Penix (jonathonpenix) July 3, 2026 08:16

Pawan Nirpal (pawan-nirpal-031) force-pushed the libcxx-tests-riscv-enablement branch from 29bd159 to 01ca187 Compare July 3, 2026 08:17

Shreeyash Pandey (bojle) reviewed Jul 3, 2026

View reviewed changes

Pawan Nirpal (pawan-nirpal-031) force-pushed the libcxx-tests-riscv-enablement branch 3 times, most recently from 21a360d to 9025c81 Compare July 3, 2026 12:18

Pankaj Gode (pgodeq) mentioned this pull request Jul 4, 2026

Enable libcxx tests for combo with Zb* and Zc* extension #465

Closed

Pawan Nirpal (pawan-nirpal-031) force-pushed the libcxx-tests-riscv-enablement branch 4 times, most recently from 58cf1bf to 4554507 Compare July 7, 2026 15:56

Pawan Nirpal (pawan-nirpal-031) force-pushed the libcxx-tests-riscv-enablement branch from 4554507 to 6558ce9 Compare July 7, 2026 17:41

Ana Pazos (apazos) reviewed Jul 7, 2026

View reviewed changes

Pawan Nirpal (pawan-nirpal-031) force-pushed the libcxx-tests-riscv-enablement branch from 6558ce9 to 91d8ccc Compare July 8, 2026 07:39

Pawan Nirpal (pawan-nirpal-031) force-pushed the libcxx-tests-riscv-enablement branch 4 times, most recently from 79a11b2 to 6b17e2d Compare July 10, 2026 09:44

Pawan Nirpal (pawan-nirpal-031) requested a review from Ana Pazos (apazos) July 10, 2026 13:52

Jonathon Penix (jonathonpenix) reviewed Jul 10, 2026

View reviewed changes

[CPULLVM] - Prepare for LIBCXX tests enablement RISCV

fa1b0cb

Signed-off-by: Pawan Nirpal <pnirpal@qti.qualcomm.com>

Pawan Nirpal (pawan-nirpal-031) force-pushed the libcxx-tests-riscv-enablement branch 3 times, most recently from fe13a13 to fa1b0cb Compare July 13, 2026 08:18

Pawan Nirpal (pawan-nirpal-031) added 3 commits July 13, 2026 19:00

Update test.sh

c9f662e

Signed-off-by: Pawan Nirpal <pnirpal@qti.qualcomm.com>

Merge branch 'qualcomm:qualcomm-software' into libcxx-tests-riscv-ena…

3c663c9

…blement

Update riscv32im_zba_zbb_zbc_zbs_zca_zcb_zcmp_ilp32_nothreads_nopic.json

217d620

Signed-off-by: Pawan Nirpal <pnirpal@qti.qualcomm.com>

Update test_libcxx.sh

1144244

Signed-off-by: Pawan Nirpal <pnirpal@qti.qualcomm.com>

Jonathon Penix (jonathonpenix) approved these changes Jul 14, 2026

View reviewed changes

Ana Pazos (apazos) merged commit 5193d63 into qualcomm:qualcomm-software Jul 14, 2026
16 of 18 checks passed

Jonathon Penix (jonathonpenix) added this to the Release 23.x milestone Aug 14, 2026

Jonathon Penix (jonathonpenix) mentioned this pull request Aug 22, 2026

[cpullvm] Add an xqci variant as part of libc++ tests #620

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