[DAG] Improved handling of ISD::ROTL and ISD::ROTR in isKnownToBeAPowerOfTwo by mirimmad · Pull Request #182744 · llvm/llvm-project

mirimmad · 2026-02-22T14:01:20Z

github-actions · 2026-02-22T14:01:38Z

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llvmbot · 2026-02-22T14:02:08Z

@llvm/pr-subscribers-backend-x86

@llvm/pr-subscribers-llvm-selectiondag

Author: Mir Immad (mirimmad)

Changes

Fixes #181642

Full diff: https://github.com/llvm/llvm-project/pull/182744.diff

2 Files Affected:

(modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (+1-2)
(modified) llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp (+49)

diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 581553d41cb6d..971c5f5674ecb 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4733,8 +4733,7 @@ bool SelectionDAG::isKnownToBeAPowerOfTwo(SDValue Val,
 
   case ISD::ROTL:
   case ISD::ROTR:
-    return isKnownToBeAPowerOfTwo(Val.getOperand(0), /*OrZero=*/false,
-                                  Depth + 1);
+    return isKnownToBeAPowerOfTwo(Val.getOperand(0), false, Depth + 1);
 
   case ISD::SMIN:
   case ISD::SMAX:
diff --git a/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp b/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
index b2b8dfb0c21fc..33a3540f6b562 100644
--- a/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
+++ b/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
@@ -1119,6 +1119,55 @@ TEST_F(AArch64SelectionDAGTest,
   EXPECT_EQ(SplatIdx, 0);
 }
 
+TEST_F(AArch64SelectionDAGTest, KnownToBeAPowerOfTwo_ROTL) {
+  SDLoc Loc;
+  auto IntVT = EVT::getIntegerVT(Context, 32);
+
+  // Power-of-two values
+  auto Pow2_4 = DAG->getConstant(4, Loc, IntVT);
+  auto Pow2_8 = DAG->getConstant(8, Loc, IntVT);
+
+  // Non-power-of-two values
+  auto NonPow2_5 = DAG->getConstant(5, Loc, IntVT);
+  auto NonPow2_0 = DAG->getConstant(0, Loc, IntVT);
+
+  auto RotAmount = DAG->getConstant(3, Loc, IntVT);
+
+  auto RotlPow2_4 = DAG->getNode(ISD::ROTL, Loc, IntVT, Pow2_4, RotAmount);
+  auto RotlPow2_8 = DAG->getNode(ISD::ROTL, Loc, IntVT, Pow2_8, RotAmount);
+  auto RotlNonPow2_5 =
+      DAG->getNode(ISD::ROTL, Loc, IntVT, NonPow2_5, RotAmount);
+  auto RotlZero = DAG->getNode(ISD::ROTL, Loc, IntVT, NonPow2_0, RotAmount);
+
+  EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(RotlPow2_4));
+  EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(RotlPow2_8));
+
+  EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(RotlNonPow2_5));
+
+  EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(RotlZero));
+  EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(RotlZero, /*OrZero=*/true));
+}
+
+TEST_F(AArch64SelectionDAGTest, KnownToBeAPowerOfTwo_ROTR) {
+  SDLoc Loc;
+  auto IntVT = EVT::getIntegerVT(Context, 32);
+
+  auto Pow2_16 = DAG->getConstant(16, Loc, IntVT);
+  auto NonPow2_6 = DAG->getConstant(6, Loc, IntVT);
+  auto Zero = DAG->getConstant(0, Loc, IntVT);
+
+  auto RotAmount = DAG->getConstant(5, Loc, IntVT);
+
+  auto RotrPow2 = DAG->getNode(ISD::ROTR, Loc, IntVT, Pow2_16, RotAmount);
+  auto RotrNonPow2 = DAG->getNode(ISD::ROTR, Loc, IntVT, NonPow2_6, RotAmount);
+  auto RotrZero = DAG->getNode(ISD::ROTR, Loc, IntVT, Zero, RotAmount);
+
+  EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(RotrPow2));
+  EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(RotrNonPow2));
+  EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(RotrZero));
+  EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(RotrZero, /*OrZero=*/true));
+}
+
 TEST_F(AArch64SelectionDAGTest, getRepeatedSequence_Patterns) {
   TargetLowering TL(*TM, *STI);

mirimmad · 2026-02-22T17:38:36Z

@RKSimon Made the changes, thanks.

mirimmad · 2026-02-24T11:22:32Z

@arsenm There are already tests for pow2_rotr and pow2_rotl in known-pow2.ll. I have added tests for the vector case.

github-actions · 2026-02-24T18:24:14Z

✅ With the latest revision this PR passed the undef deprecator.

RKSimon · 2026-02-25T11:42:15Z

@@ -11,6 +11,8 @@ declare i32 @llvm.smin.i32(i32, i32)
 declare i32 @llvm.smax.i32(i32, i32)
 declare i32 @llvm.fshl.i32(i32, i32, i32)
 declare i32 @llvm.fshr.i32(i32, i32, i32)
+declare <2 x i32> @llvm.fshl.v2i32(<2 x i32>, <2 x i32>, <2 x i32>)
+declare <2 x i32> @llvm.fshr.v2i32(<2 x i32>, <2 x i32>, <2 x i32>)


don't bother adding these - we don't need to declare anymore

RKSimon · 2026-02-25T11:42:34Z

@@ -889,3 +891,32 @@ define i1 @pow2_and_i128(i128 %num, i128 %shift) {
  %bool = icmp eq i128 %bit, 0
  ret i1 %bool
 }
+
+define <2 x i32> @pow2_rotl_vec() {


Use the update_llc_test_checks script

…erOfTwo' and associated tests

Use zeroinitializer instead of undef.

RKSimon

Please fix the bad merge (test files?)

github-actions · 2026-03-03T10:42:53Z

🪟 Windows x64 Test Results

131798 tests passed
2974 tests skipped

✅ The build succeeded and all tests passed.

github-actions · 2026-03-03T10:42:53Z

🐧 Linux x64 Test Results

191565 tests passed
4986 tests skipped

✅ The build succeeded and all tests passed.

RKSimon

LGTM - cheers

github-actions · 2026-03-04T16:43:46Z

@mirimmad Congratulations on having your first Pull Request (PR) merged into the LLVM Project!

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…erOfTwo (llvm#182744) Fixes llvm#181642

llvmbot added the llvm:SelectionDAG SelectionDAGISel as well label Feb 22, 2026

RKSimon self-requested a review February 22, 2026 15:48

RKSimon requested changes Feb 22, 2026

View reviewed changes

Comment thread llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Outdated

arsenm reviewed Feb 23, 2026

View reviewed changes

Comment thread llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp Outdated

arsenm reviewed Feb 23, 2026

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Comment thread llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp Outdated

llvmbot added the backend:X86 label Feb 24, 2026

mirimmad requested review from RKSimon and arsenm February 24, 2026 12:13

topperc reviewed Feb 24, 2026

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Comment thread llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp Outdated

RKSimon requested changes Feb 25, 2026

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mirimmad requested a review from RKSimon February 27, 2026 05:19

RKSimon mentioned this pull request Mar 1, 2026

[DAG] isKnownToBeAPowerOfTwo - Power of 2 value is known to be power of 2 after BSWAP/BITREVERSE #182207

Merged

mirimmad added 5 commits March 2, 2026 14:59

use 'OrZero' in 'isKnownToBeAPowerOfTwo'

15e6b60

Add a test for ISD::ROTL and ISD::ROTR

1bd6086

Add missing 'DemandedElts' and 'OrZero' arguments to 'isKnownToBeAPow…

f105d54

…erOfTwo' and associated tests

Remove 'auto' and add a test for vector case

092f134

Use 'SELECT' when creating ROTL/ROTR nodes

f3a380f

Use zeroinitializer instead of undef.

mirimmad force-pushed the main branch from 468330e to 793fb62 Compare March 2, 2026 09:55

RKSimon requested changes Mar 2, 2026

View reviewed changes

mirimmad force-pushed the main branch from fb9b828 to 52c1aeb Compare March 2, 2026 10:02

mirimmad requested a review from RKSimon March 2, 2026 10:07

mirimmad force-pushed the main branch 2 times, most recently from 5b0ac03 to 97e2eb2 Compare March 2, 2026 10:57

Add test for handling DemandElts for vectors in ROTL and ROTR

ee5726e

mirimmad force-pushed the main branch from 97e2eb2 to ee5726e Compare March 2, 2026 11:01

RKSimon requested changes Mar 2, 2026

View reviewed changes

Perform 'rot' on vectors and remove unittests

7ee0aa5

mirimmad requested a review from RKSimon March 3, 2026 06:54

arsenm reviewed Mar 3, 2026

View reviewed changes

Comment thread llvm/test/CodeGen/X86/known-pow2.ll

reformat: ignore col80 and use single lines

e6fe1d0

RKSimon requested changes Mar 3, 2026

View reviewed changes

Comment thread llvm/test/CodeGen/X86/known-pow2.ll Outdated

Comment thread llvm/test/CodeGen/X86/known-pow2.ll

Comment thread llvm/test/CodeGen/X86/known-pow2.ll Outdated

Store the vector to avoid scalarisation, use 'urem' for comparision

a95653f

mirimmad force-pushed the main branch from a1f251e to a95653f Compare March 3, 2026 10:44

update known-pow2.ll with update_llc_test_checks.py

446555d

mirimmad force-pushed the main branch from 144b09e to 446555d Compare March 3, 2026 10:54

Merge branch 'main' into main

0f47669

mirimmad requested a review from RKSimon March 4, 2026 05:49

upadate known-pow2.ll wihth update_llc_test_checks.py

f9c2d03

RKSimon approved these changes Mar 4, 2026

View reviewed changes

Merge branch 'main' into main

b502d7d

RKSimon enabled auto-merge (squash) March 4, 2026 16:08

RKSimon merged commit b0b5834 into llvm:main Mar 4, 2026
10 checks passed

sujianIBM pushed a commit to sujianIBM/llvm-project that referenced this pull request Mar 5, 2026

[DAG] Improved handling of ISD::ROTL and ISD::ROTR in isKnownToBeAPow…

29ae69d

…erOfTwo (llvm#182744) Fixes llvm#181642

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